Abstract: A method for detecting a memory chip includes the following steps coupling a detecting circuit to a first area and a second area of the memory chip, the second area is not overlapped with the first area; inputting a first detecting signal from the detecting circuit to the first area of the memory chip; burning out a cell of the detecting circuit; and inputting a second detecting signal from the detecting circuit to the second area of the memory chip.

Abstract: The present application provides a memory test circuit and a device wafer including the memory test circuit. The memory test circuit is coupled to a memory array having intersecting first and second signal lines, and includes a fuse element and a transistor. The fuse element has a first terminal coupled to a first group of the first signal lines and a test voltage, and has a second terminal coupled to second and third groups of the first signal lines. The transistor has a source/drain terminal coupled to the second terminal of the fuse element and another source/drain terminal coupled to a reference voltage. The first group of the first signal lines are selectively coupled to the test voltage when the transistor is turned on, and all of the first signal lines are coupled to the test voltage when the transistor is kept off.

Abstract: The present disclosure provides a method for preparing a semiconductor device. The semiconductor device includes a substrate, a first region, a second region, a third region, a fourth region, a fifth region and a sixth region. The first type region is disposed on the substrate and has a ring structure. The second type region is disposed on the substrate and disposed in the center of the first type region. A plurality of second well regions are formed in the first region, the second region, the fourth region, the fifth region and the sixth region. A plurality of second well regions in the first region, the second region, the fourth region, the fifth region and the sixth region. The first well region, the second well region, the first type region and the second type region are formed by ion implantation.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a first bit line structure positioned above the substrate and including a first line portion arranged in parallel to a first direction, and a second line portion connecting to a first end of the first line portion and arranged in parallel to a second direction in perpendicular to the first direction; a first bit line top contact including a first bar portion positioned on the first end of the first line portion and arranged in parallel to the first direction, and a second bar portion connecting to a first end of the first bar portion, positioned on the second line portion, and arranged in parallel to the second direction; and a first top conductive layer electrically coupled to the first bit line top contact.

Abstract: The present disclosure provides a semiconductor structure having a test structure. The semiconductor structure includes a semiconductor substrate, a memory device and a test structure. The memory device is disposed on the semiconductor substrate, and includes a device area and an edge area. The edge area surrounds the device area. The test structure is disposed on the semiconductor substrate, and includes a dummy area, a test edge area and a plurality of unit cells. The test edge area surrounds the dummy area. The unit cells have a first group disposed in the dummy area and a second group disposed in the test edge area. The second group of unit cells includes the outermost unit cells of the plurality of unit cells. A shape surrounded by the edge area in a top view is different from a shape surrounded by the test edge area in the top view.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first testing area, a word line structure positioned in the first testing area and arranged parallel to a first axis, a first column of capacitor contact structures positioned in the first testing area and arranged parallel to a second axis perpendicular to the first axis, a second column of capacitor contact structures positioned adjacent to the first column of capacitor contact structures and arranged parallel to the first column of capacitor contact structures, and a first testing structure including a first drain portion extended along the second axis and a first source portion extended along the second axis. The first drain portion is positioned on the first column of capacitor contact structures and the first source portion is positioned on the second column of capacitor contact structures.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first testing area, a word line structure positioned in the first testing area and arranged parallel to a first axis, a first column of capacitor contact structures positioned in the first testing area and arranged parallel to a second axis perpendicular to the first axis, a second column of capacitor contact structures positioned adjacent to the first column of capacitor contact structures and arranged parallel to the first column of capacitor contact structures, and a first testing structure including a first drain portion extended along the second axis and a first source portion extended along the second axis. The first drain portion is positioned on the first column of capacitor contact structures and the first source portion is positioned on the second column of capacitor contact structures.

Abstract: The present disclosure provides a semiconductor structure having a test structure. The semiconductor structure includes a semiconductor substrate, a memory device and a test structure. The memory device is disposed on the semiconductor substrate, and includes a device area and an edge area. The edge area surrounds the device area. The test structure is disposed on the semiconductor substrate, and includes a dummy area, a test edge area and a plurality of unit cells. The test edge area surrounds the dummy area. The plurality of unit cells are disposed in the test edge area, and the dummy area is free of the unit cells. A dimension of the test edge area in a top view is different from a dimension of the edge area in the top view.

Abstract: The present disclosure provides a testing fixture. The testing fixture includes a carrier, a plurality of sets of electrical lines and a plurality of electrical lines. The carrier includes a base and a frame extending along an upper surface of the base. The base and the frame define a first recess, a second recess extending longitudinally from the first recess, and a third recess extending transversely from the first recess. The plurality of sets of electrical contacts are disposed on the base and arranged in a rotationally symmetrical manner, and the electrical lines are electrically connected to the plurality of sets of electrical contacts.

Abstract: The present disclosure provides a semiconductor structure having a test structure. The semiconductor structure includes a semiconductor substrate, a memory device and a test structure. The memory device is disposed on the semiconductor substrate, and includes a device area and an edge area. The edge area surrounds the device area. The test structure is disposed on the semiconductor substrate, and includes a dummy area, a test edge area and a plurality of unit cells. The test edge area surrounds the dummy area. The unit cells have a first group disposed in the dummy area and a second group disposed in the test edge area. The second group of unit cells includes the outermost unit cells of the plurality of unit cells. A shape surrounded by the edge area in a top view is different from a shape surrounded by the test edge area in the top view.

Abstract: A test array structure includes a substrate, first and second cells, first and second bit-line rings and four word-lines. Each of the first and second cells has a first drain region, a first gate region, a source region, a second gate region and a second drain region connected together in sequence. The first drain region and the first gate region of the first cell are located within the first bit-line ring. The second drain region and the second gate region of the first cell are located between the first and second bit-line rings. The first drain region and the first gate region of the second cell is located within the second bit-line ring. The second drain region of the first cell and the first drain region of the second cell are located between the two immediately-adjacent word-lines.

Abstract: The present disclosure provides a testing fixture for holding a device under test (DUT). The testing fixture includes a base, a frame, a recessed portion, a plurality of sets of electrical contacts and a plurality of electrical lines. The frame extends upward along an outer perimeter of an upper surface of the base. The recessed portion is surrounded by the frame and the upper surface of the base, and the DUT is received in the recessed portion. The plurality of sets of electrical contacts are disposed on the recessed portion and arranged in a rotationally symmetrical manner, wherein a plurality of plated through holes of the DUT are in contact with one set of the electrical contacts after the DUT is assembled with the testing fixture.

Abstract: A test array structure includes a substrate, first and second cells, first and second bit-line rings and four word-lines. Each of the first and second cells has a first drain region, a first gate region, a source region, a second gate region and a second drain region connected together in sequence. The first drain region and the first gate region of the first cell are located within the first bit-line ring. The second drain region and the second gate region of the first cell are located between the first and second bit-line rings. The first drain region and the first gate region of the second cell is located within the second bit-line ring. The second drain region of the first cell and the first drain region of the second cell are located between the two immediately-adjacent word-lines.

Abstract: A testing structure is disclosed. The testing structure includes a first layer, a second layer, and a third layer. The first layer includes a first pattern. The third layer includes a second pattern. The first layer, the second layer, and the third layer overlap each other. The second layer is connected to a CBCM (charged based capacitance measurement) testing circuit.

Abstract: The present disclosure provides a method for preparing a semiconductor device. The semiconductor device includes a substrate, a first region, a second region, a third region, a fourth region, a fifth region and a sixth region. The first type region is disposed on the substrate and has a ring structure. The second type region is disposed on the substrate and disposed in the center of the first type region. A plurality of second well regions are formed in the first region, the second region, the fourth region, the fifth region and the sixth region. A plurality of second well regions in the first region, the second region, the fourth region, the fifth region and the sixth region. The first well region, the second well region, the first type region and the second type region are formed by ion implantation.

Abstract: A method includes forming a transistor over a substrate; forming a conductive structure over the substrate, such that a first end of the conductive structure is electrically coupled to a gate of the transistor, and a second end of the conductive structure is electrically coupled to the substrate; applying biases to the gate of the transistor and source/drain structures of the transistor; determining whether the first end and the second end of the conductive structure are electrically connected; generating, based on the determination, a first result indicating that the first end and the second end of the conductive structure are electrically connected; and qualifiying the conductive structure as an antenna in response to the first result.

Abstract: The present disclosure provides a testing fixture. The testing fixture includes a carrier, a plurality of sets of electrical lines and a plurality of electrical lines. The carrier includes a base and a frame extending along an upper surface of the base. The base and the frame define a first recess, a second recess extending longitudinally from the first recess, and a third recess extending transversely from the first recess. The plurality of sets of electrical contacts are disposed on the base and arranged in a rotationally symmetrical manner, and the electrical lines are electrically connected to the plurality of sets of electrical contacts.

Abstract: The present disclosure provides a testing fixture for holding a device under test (DUT). The testing fixture includes a base, a frame, a recessed portion, a plurality of sets of electrical contacts and a plurality of electrical lines. The frame extends upward along an outer perimeter of an upper surface of the base. The recessed portion is surrounded by the frame and the upper surface of the base, and the DUT is received in the recessed portion. The plurality of sets of electrical contacts are disposed on the recessed portion and arranged in a rotationally symmetrical manner, wherein a plurality of plated through holes of the DUT are in contact with one set of the electrical contacts after the DUT is assembled with the testing fixture.

Abstract: The present disclosure provides a semiconductor device and a method for preparing the same. The semiconductor device includes a substrate, a first type region, and a second type region. The first type region is disposed on the substrate and has a ring structure. The second type region is disposed on the substrate and disposed in the center of the first type region. The second type region has a square shape and includes a plurality of corners.

Abstract: A testing structure is disclosed. The testing structure includes a first layer, a second layer, and a third layer. The first layer includes a first pattern. The third layer includes a second pattern. The first layer, the second layer, and the third layer overlap each other. The second layer is connected to a CBCM (charged based capacitance measurement) testing circuit.