Abstract: A method includes forming a transistor over a substrate; forming a conductive structure over the substrate, such that a first end of the conductive structure is electrically coupled to a gate of the transistor, and a second end of the conductive structure is electrically coupled to the substrate; applying biases to the gate of the transistor and source/drain structures of the transistor; determining whether the first end and the second end of the conductive structure are electrically connected; generating, based on the determination, a first result indicating that the first end and the second end of the conductive structure are electrically connected; and qualifiying the conductive structure as an antenna in response to the first result.

Abstract: A holder includes a substrate, at least one first fastener and a pressure block. The substrate includes a top surface, a primary recess recessed from the top surface, at least one first side-recess recessed from the top surface, wherein the first side-recess neighbors and communicates with the primary recess, and a channel recess recessed from the top surface, wherein the channel recess neighbors and communicates with the primary recess, and the first side-recess and the channel recess are positioned at opposite sides of the primary recess. The first fastener is disposed in the first side-recess, wherein the first fastener has a top substantially leveled with the top surface of the substrate. The pressure block is disposed in the channel recess, wherein the pressure block has a top substantially leveled with the top surface of the substrate.

Abstract: A method includes forming a transistor over a substrate; forming a conductive structure over the substrate, such that a first end of the conductive structure is electrically coupled to a gate of the transistor, and a second end of the conductive structure is electrically coupled to the substrate; applying biases to the gate of the transistor and source/drain structures of the transistor; determining whether the first end and the second end of the conductive structure are electrically connected; generating, based on the determination, a first result indicating that the first end and the second end of the conductive structure are electrically connected; and qualifying the conductive structure as an antenna in response to the first result.

Abstract: An integrated circuit device is disclosed. The integrated circuit device includes a capacitor array, a decoder circuit, and an integrated circuit. The capacitor array includes a plurality of capacitor units. The decoder circuit is coupled to the capacitor array. The integrated circuit is coupled to the decoder circuit. The decoder circuit is configured to conduct part of the plurality of capacitor units, and to un-conduct part of the plurality of capacitor units, so as to adjust a capacitance value coupled to the integrated circuit.

Abstract: An anti-fuse structure includes an active area, a gate electrode over the active area, and a dielectric layer between the active area and the gate electrode. The active area and the gate electrode partially overlap in a vertical projection direction, forming a plurality of channels. One of the gate electrode and the active area includes a plurality of extending portions to form the plurality of channels.

Abstract: A semiconductor structure includes a first anti-fuse structure, a second anti-fuse structure and a first metal layer. The second anti-fuse structure is disposed over the first anti-fuse structure. The first metal layer is between the first anti-fuse structure and the second anti-fuse structure. A first contact is disposed between the first anti-fuse structure and the first metal layer to connect thereof. A second contact is disposed between the second anti-fuse structure and the first metal layer to connect thereof.

Abstract: A holder includes a substrate, at least one first fastener and a pressure block. The substrate includes a top surface, a primary recess recessed from the top surface, at least one first side-recess recessed from the top surface, wherein the first side-recess neighbors and communicates with the primary recess, and a channel recess recessed from the top surface, wherein the channel recess neighbors and communicates with the primary recess, and the first side-recess and the channel recess are positioned at opposite sides of the primary recess. The first fastener is disposed in the first side-recess, wherein the first fastener has a top substantially leveled with the top surface of the substrate. The pressure block is disposed in the channel recess, wherein the pressure block has a top substantially leveled with the top surface of the substrate.

Abstract: A semiconductor structure includes a first anti-fuse structure, a second anti-fuse structure and a first metal layer. The second anti-fuse structure is disposed over the first anti-fuse structure. The first metal layer is between the first anti-fuse structure and the second anti-fuse structure. A first contact is disposed between the first anti-fuse structure and the first metal layer to connect thereof. A second contact is disposed between the second anti-fuse structure and the first metal layer to connect thereof.

Abstract: The present disclosure provides a semiconductor device and a method for preparing the same. The semiconductor device includes a substrate, a first type region, and a second type region. The first type region is disposed on the substrate and has a ring structure. The second type region is disposed on the substrate and disposed in the center of the first type region. The second type region has a square shape and includes a plurality of corners.

Abstract: A method includes forming a transistor over a substrate; forming a conductive structure over the substrate, such that a first end of the conductive structure is electrically coupled to a gate of the transistor, and a second end of the conductive structure is electrically coupled to the substrate; applying biases to the gate of the transistor and source/drain structures of the transistor; determining whether the first end and the second end of the conductive structure are electrically connected; generating, based on the determination, a first result indicating that the first end and the second end of the conductive structure are electrically connected; and qualifying the conductive structure as an antenna in response to the first result.

Abstract: An electronic device includes a substrate, an electronic component disposed over the substrate and an electrical testing component disposed over the substrate. The electronic component includes a bottom plate over the substrate, and a top plate over the bottom plate. The electrical testing component includes a first anti-fuse structure and a second anti-fuse structure, wherein the first anti-fuse structure and the second anti-fuse structure are electrically connected to the bottom plate.

Abstract: An electronic device includes a substrate, an electronic component disposed over the substrate and an electrical testing component disposed over the substrate. The electronic component includes a bottom plate over the substrate, and a top plate over the bottom plate. The electrical testing component includes a first anti-fuse structure and a second anti-fuse structure, wherein the first anti-fuse structure and the second anti-fuse structure are electrically connected to the bottom plate.

Abstract: An anti-fuse structure includes an active area, a gate electrode over the active area, and a dielectric layer between the active area and the gate electrode. The active area and the gate electrode partially overlap in a vertical projection direction, forming a plurality of channels. One of the gate electrode and the active area includes a plurality of extending portions to form the plurality of channels.

Abstract: An anti-fuse structure includes an active area, a gate electrode over the active area, and a dielectric layer between the active area and the gate electrode. The active area and the gate electrode partially overlap in a vertical projection direction, forming a plurality of channels. One of the gate electrode and the active area includes a plurality of extending portions to form the plurality of channels.