Patents by Inventor Jui Huang

Jui Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240412390
    Abstract: A method for image alignment is provided. The method for image alignment includes the following stages. A first image with a first property from a first sensor is received. A second image with a second property from a second sensor is received. The first property is similar to the second property. The first feature correspondence between the first image and the second image is calculated. A third image with a third property from the first sensor and a fourth image with a fourth property from the second image sensor are received. The third property is different from the fourth property. Image alignment is performed on the third image and the fourth image based on the first feature correspondence between the first image and the second image.
    Type: Application
    Filed: June 8, 2023
    Publication date: December 12, 2024
    Inventors: Yen-Yang CHOU, Keh-Tsong LI, Shao-Yang WANG, Chia-Hui KUO, Hung-Chih KO, Pin-Wei CHEN, Yu-Hua HUANG, Yun-I CHOU, Chien-Ho YU, Chi-Cheng JU, Ying-Jui CHEN
  • Publication number: 20240404019
    Abstract: An image processing method is provided. The method includes the step of comparing each of the input pixels in an input image to a corresponding buffered pixel in a buffered image, and computing the difference value between the input pixel value of the input pixel and the buffered pixel value of the buffered pixel. The method further includes the step of generating a blended image based on the input pixel values and the corresponding difference values. The method further includes the step of determining whether a criterion associated with the difference value is met, for each of the difference values. The method further includes the step of updating, for each of the buffered pixels in the buffered image, the buffered pixel value based on the corresponding input pixel value if the criterion is met, and keeping the buffered pixel value unchanged if the criterion is not met.
    Type: Application
    Filed: May 29, 2023
    Publication date: December 5, 2024
    Inventors: Cheng-Yu SHIH, Hao-Tien CHIANG, Yuan-Chen CHENG, Ying-Wei WU, Tai-Hsiang HUANG, Ying-Jui CHEN, Chi-Cheng JU
  • Publication number: 20240397621
    Abstract: A circuit board device includes a transition region that includes a first conductive layer at a first level, a second conductive layer at a second level, and conductive vias. The first conductive layer includes a pad connected to the solderless connector, a transmission line, and a first reference layer. The transmission line includes first and second segments. A second width of the second segment is the same as or less than a first width of the first segment. The first reference layer has a first anti-pad region for the pad and the transmission line disposed therein. In a plan view, the first anti-pad region surrounding the pad is completely located within a second anti-pad region of a second reference layer of the second conductive layer. The conductive vias are disposed between the first and second conductive layers and surround the pad.
    Type: Application
    Filed: June 30, 2023
    Publication date: November 28, 2024
    Applicants: UNIMICRON TECHNOLOGY CORP., National Taiwan University
    Inventors: Chin-Hsun WANG, Ruey-Beei WU, Chun-Jui HUANG, Wei-Yu LIAO, Ching-Sheng CHEN, Chi-Min CHANG
  • Publication number: 20240397187
    Abstract: A method for tuning a plurality of image signal processor (ISP) parameters of a camera includes performing a first iteration. The first iteration includes extracting image features from an initial image, arranging a tuning order of the plurality of ISP parameters of the camera according to at least the plurality of ISP parameters and the image features, tuning a first set of the ISP parameters according to the tuning order to generate a first tuned set of the ISP parameters, and replacing the first set of the ISP parameters with the first tuned set of the ISP parameters in the plurality of ISP parameters to generate a plurality of updated ISP parameters.
    Type: Application
    Filed: May 23, 2023
    Publication date: November 28, 2024
    Applicant: MEDIATEK INC.
    Inventors: Tsung-Han Chan, Yi-Hsuan Huang, Hsiao-Chien Yang, Ding-Yun Chen, Yi-Ping Liu, Chin-Yuan Tseng, Ming-Feng Tien, Shih-Hung Liu, Shuo-En Chang, Yu-Chuan Chuang, Cheng-Tsai Ho, Ying-Jui Chen, Chi-Cheng Ju
  • Publication number: 20240396350
    Abstract: A power supply circuit is adapted to an electronic device. The power supply circuit includes a drive circuit, a feedback resistor circuit, a battery module and a controller. The drive circuit receives a charger boost indication signal and generates a drive signal accordingly. The feedback resistor circuit has a feedback resistance value changing in response to the drive signal and receives a DC power supply to supply power to a system component. The battery module provides a battery power supply to the system component. The controller controls the battery power supply provided by the battery module according to the feedback resistance value. When the system component is operating in a heavy load state, the controller transmits the corresponding charger boost indication signal to the drive circuit, so as to reduce the feedback resistance value through the drive signal.
    Type: Application
    Filed: January 29, 2024
    Publication date: November 28, 2024
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Bo-Siang Cheng, Hsiang-Jui Hung, Sheng-Chieh Su, Min-Hou Kuo, Jia-Ching Huang, Yen-Yong Wu
  • Patent number: 12144555
    Abstract: An augmented reality-assisted method for performing surgery comprises: disposing a position sensing element at a facial positioning point of a patient before craniotomy to obtain skull space and intracranial space information for defining a coordinate space; obtaining a brain anatomical image for constructing a three-dimensional graphic, the graphic comprising a graphic positioning point and a feature associated with a gyrus feature; defining a relative positional relationship between the graphic and the space, aligning the facial positioning point with the graphic positioning point; using a probe to obtain a spatial position of the gyrus feature after craniotomy, using the gyrus feature as a calibration reference point; generating a displacement and rotation parameter based on a coordinate difference of the feature relative to the reference point; adjusting a position and/or an angle of the graphic on a display according to the parameter, and the display displaying the calibrated three-dimensional graphic.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: November 19, 2024
    Assignee: MEDICALTEK CO., LTD.
    Inventors: Yen-Yu Wang, Shu-Jui Hsieh, Jing-Ying Huang
  • Publication number: 20240377762
    Abstract: A semiconductor substrate stage for carrying a substrate is provided. The semiconductor substrate stage includes a carrier layer, a storage layer having an energy storage device and a water storage device, a magnetic shielding layer disposed between the carrier layer and the storage layer, and a receiver disposed in a recess of the carrier layer and partially exposed from the carrier layer.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Yu-Huan CHEN, Yu-Chih HUANG, Ya-An PENG, Shang-Chieh CHIEN, Li-Jui CHEN, Heng-Hsin LIU
  • Publication number: 20240375585
    Abstract: A system for imaging at least one of a trailer or other conveyance that is connected to a tractor and an environment proximate the tractor, wherein the trailer or other conveyance has two opposed lateral sides, the system comprising a plurality of sensors mounted to the tractor, wherein the sensors together have an active sensing area that encompasses at least the two opposed lateral sides of the trailer or other conveyance.
    Type: Application
    Filed: May 12, 2023
    Publication date: November 14, 2024
    Inventors: Frederick M. Moore, Yibiao Zhao, Ripudaman Singh Arora, Hung-Jui Huang
  • Publication number: 20240372476
    Abstract: A bidirectional power supply includes an alternating current (AC) port as a source in a first mode and as a load in a second mode and a line-frequency rectifier/inverter to function as a rectifier in the first mode and a set of switches to function as an inverter in the second mode. A bidirectional resonant converter is coupled to a direct current (DC) port with primary-side switches and secondary-side switches respectively arranged on a primary and secondary side of a transformer. A controller controls the primary-side switches and the secondary-side switches by controlling switching frequency based on a determined value while setting time delay between control of the primary-side and the secondary-side switches to be a predefined time delay or by controlling the time delay between control of the primary-side and the secondary-side switches based on a determined value while setting the switching frequency to be a predefined switching frequency.
    Type: Application
    Filed: May 3, 2023
    Publication date: November 7, 2024
    Applicant: Delta Electronics, Inc.
    Inventors: Misha Kumar, Peter Mantovanelli Barbosa, Sergio Fernandez Rojas, Chao-Jui Huang
  • Publication number: 20240363343
    Abstract: A method includes following steps. A single-crystalline two-dimensional (2D) semiconductor layer is formed over a substrate. A single-crystalline 2D material layer is epitaxially grown on the single-crystalline 2D semiconductor layer. The single-crystalline 2D material layer is lattice-matched with the single-crystalline 2D semiconductor layer. A semiconductor device is over the single-crystalline 2D semiconductor layer.
    Type: Application
    Filed: April 27, 2023
    Publication date: October 31, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., National Yang Ming Chiao Tung University
    Inventors: Shu-Jui CHANG, Shin-Yuan WANG, Yu-Che HUANG, Chao-Hsin CHIEN, Chenming HU
  • Patent number: 12133323
    Abstract: A transmission device for suppressing the glass-fiber effect includes a circuit board and a transmission line. The circuit board includes a plurality of glass fibers, so as to define a fiber pitch. The transmission line is disposed on the circuit board. The transmission line includes a plurality of non-parallel segments. Each of the non-parallel segments of the transmission line has an offset distance with respect to a reference line. The offset distance is longer than or equal to a half of the fiber pitch.
    Type: Grant
    Filed: November 23, 2022
    Date of Patent: October 29, 2024
    Assignees: UNIMICRON TECHNOLOGY CORP., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chin-Hsun Wang, Ruey-Beei Wu, Ching-Sheng Chen, Chun-Jui Huang, Wei-Yu Liao, Chi-Min Chang
  • Publication number: 20240355953
    Abstract: A photovoltaic cell includes a germanium-containing well embedded in a single crystalline silicon substrate and extending to a proximal horizontal surface of the single crystalline silicon substrate, wherein germanium-containing well includes germanium at an atomic percentage greater than 50%. A silicon-containing capping structure is located on a top surface of the germanium-containing well and includes silicon at an atomic percentage greater than 42%. The silicon-containing capping structure prevents oxidation of the germanium-containing well. A photovoltaic junction may be formed within, or across, the trench by implanting dopants of a first conductivity type and dopants of a second conductivity type.
    Type: Application
    Filed: June 27, 2024
    Publication date: October 24, 2024
    Inventors: Jyh-Ming HUNG, Tzu-Jui WANG, Kuan-Chieh HUANG, Jhy-Jyi SZE
  • Publication number: 20240355859
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a first IC chip bonded to a second IC chip. The first IC chip includes a plurality of photodetectors disposed in a first substrate and a first bond structure. The first bond structure includes a first plurality of bond contacts disposed on a first plurality of conductive bond pads. The second IC chip includes a second bond structure and a second substrate. A first bond interface is disposed between the first bond structure and the second bond structure. The second bond structure comprises a second plurality of bond contacts. The first bond structure further includes a first plurality of shield structures disposed between adjacent conductive bond pads in the first plurality of conductive bond pads.
    Type: Application
    Filed: April 19, 2023
    Publication date: October 24, 2024
    Inventors: Hao-Lin Yang, Kuan-Chieh Huang, Wei-Cheng Hsu, Tzu-Jui Wang, Chen-Jong Wang, Dun-Nian Yaung
  • Publication number: 20240355639
    Abstract: A package structure and a method of manufacturing the same are provided. The method of manufacturing the package structure includes several steps as follows. A lead frame is provided. A first mask layer is formed on an upper surface of the lead frame and a second mask layer is formed on a lower surface of the lead frame, so that the first mask layer, the lead frame and the second mask layer are formed together to be a multilayered structure. A patterning process is performed on the multilayered structure, so a through hole penetrating through the multilayered structure is formed. A sandblasting process is performed in the through hole to form a rough textured surface in the through hole. After that, the first mask layer and the second mask layer are removed to expose the upper surface and the lower surface of the lead frame.
    Type: Application
    Filed: October 16, 2023
    Publication date: October 24, 2024
    Inventors: Chin-Jui YU, Jheng-Dong HUANG, Yin-Hsien YANG, Jian-Tsai CHANG
  • Publication number: 20240355684
    Abstract: A wafer stacking method includes the following steps. A first wafer is provided. A second wafer is bonded to the first wafer to form a first wafer stack structure. A first edge defect inspection is performed on the first wafer stack structure to find a first edge defect and measure a first distance in a radial direction between an edge of the first wafer stack structure and an end of the first edge defect away from the edge of the first wafer stack structure. A first trimming process with a range of a first width is performed from the edge of the first wafer stack structure to remove the first edge defect. Herein, the first width is greater than or equal to the first distance.
    Type: Application
    Filed: May 4, 2023
    Publication date: October 24, 2024
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chih Feng Sung, Wei Han Huang, Ming-Jui Tsai, Yu Chi Chen, Yung-Hsiang Chang, Chun-Lin Lu, Shih-Ping Lee
  • Patent number: 12127392
    Abstract: A method of fabricating the semiconductor device includes forming a bit line structure over a substrate, forming a spacer structure on a sidewall of the bit line structure, partially removing an upper portion of the spacer structure to form a slope on the spacer structure slanting to the bit line structure, forming a landing pad material to cover the spacer structure and contact the slope, and removing at least a portion of the landing pad material to form a landing pad against the slope.
    Type: Grant
    Filed: October 12, 2023
    Date of Patent: October 22, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chih-Wei Huang, Hsu-Cheng Fan, En-Jui Li, Chih-Yu Yen
  • Publication number: 20240347340
    Abstract: An epitaxial structure includes a substrate and a dielectric layer. The dielectric layer is on the substrate. The substrate comprises a single crystal metal or a single crystal 2D material. The dielectric layer is in physical contact with the substrate. The dielectric layer comprises a non-perovskite structure with defined grain orientation with ferroelectric (FE) phase or antiferroelectric (AFE) phase.
    Type: Application
    Filed: April 12, 2023
    Publication date: October 17, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Shu-Jui CHANG, Shin-Yuan WANG, Yu-Che HUANG, Chao-Hsin CHIEN, Chenming HU
  • Publication number: 20240347576
    Abstract: Various embodiments of the present disclosure relate to an interstitial stacked-integrated-circuit interface shielding structure. A first integrated circuit (IC) chip includes a first dielectric layer. A second IC chip is bonded to the first IC chip at a bond interface and includes a second dielectric layer directly contacting the first dielectric layer at the bond interface. A first pair of conductive pads are respectively in the first and second dielectric layers and directly contacting at the bond interface. A second pair of conductive pads are respectively in the first and second dielectric layers and directly contacting at the bond interface. A pair of shield structures are respectively in the first and second dielectric layers and directly contact at the bond interface. Further, the pair of shield structures separate the first pair of conductive pads from the second pair of conductive pads.
    Type: Application
    Filed: April 17, 2023
    Publication date: October 17, 2024
    Inventors: Hao-Lin Yang, Kuan-Chieh Huang, Wei-Cheng Hsu, Tzu-Jui Wang, Chen-Jong Wang, Dun-Nian Yaung
  • Patent number: 12119496
    Abstract: Present invention is related to a composite modified layer attached on a current collector comprising a lithiophilic particle being covered or coated by a polymer layer. The composite modified layer further could be coated with an additional carbon layer or artificial protective film as several suitable embodiments presented in this invention. The lithiophilic particle, such as sliver nano-particle, will firstly form a lithium-silver alloys to reduce a thermodynamic instability during the growth of lithium nuclei. The sliver nano-particle is able to be attached securely on the current collector by the polymer with high adhesion ability. The fuel cell including the composite modified layer in the present invention has higher average Coulombic efficiency and higher capacity retention.
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: October 15, 2024
    Assignee: National Taiwan University of Science and Technology
    Inventors: Bing-Joe Hwang, Wei-Nien Su, Shi-Kai Jiang, Chen-Jui Huang, Sheng-Chiang Yang
  • Publication number: 20240338804
    Abstract: A method for high dynamic range imaging is provided. The method includes the following stages. A first image from a first sensor capable of sensing a first spectrum is received. A second image from a second sensor capable of sensing a second spectrum is received. The second spectrum has a higher wavelength range as compared to the first spectrum. A first image feature from the first image and a second image feature from the second image are retrieved. The first and second images are fused by referencing the first image feature and the second image feature to generate a final image.
    Type: Application
    Filed: April 6, 2023
    Publication date: October 10, 2024
    Inventors: Pin-Wei CHEN, Keh-Tsong LI, Shao-Yang WANG, Chia-Hui KUO, Hung-Chih KO, Yun-I CHOU, Yu-Hua HUANG, Yen-Yang CHOU, Chien-Ho YU, Chi-Cheng JU, Ying-Jui CHEN