Abstract: A vehicular lamp includes a housing having a chamber. The housing includes a heat dissipating portion made of metal. The housing further includes a platform integrally formed with the heat dissipating portion. The platform includes a coupling portion. A reflective cover is mounted in the chamber and includes a recessed portion in. The recessed portion has a rear end with an opening. The platform extends through the opening, and the coupling portion is received in the recessed portion. The recessed portion includes a reflective face. A light-emitting diode unit includes a plurality of light-emitting diodes fixed to the coupling portion and a circuit board fixed to the coupling portion. The light-emitting diodes emit light rays towards the reflective face of the reflective cover. A shield is mounted in front of the housing and is transmittable to the light rays.

Abstract: A cyclic comparison method for an LDPC decoder. The nth element of the input k elements, wherein n=1, . . . , k, is sequentially removed by the corresponding comparator to obtain k first level sequences. Next, pairs of two elements selected from the k elements are used to form k second level sequences. The preceding step is repeated k×?log2(k?1)? times to obtain k output results. Either of one first level sequences and one output results contains (k?1) elements. The first level sequences are compared with the output results to determine whether they are identical. If they are identical, the process stops. If they are not identical, the abovementioned step is repeated to obtain new output results. The cyclic comparison method of the present invention needs only k×?log2(k?1)? comparisons to obtain output results. Thus, the present invention can reduce the number of basic operations and can apply to any input number.

Abstract: The present invention discloses a set-cyclic comparison method for an LDPC (Low-Density Parity-Check) decoder, which applies to a CNU (Check Node Unit) or a VNU (Variable Node Unit). In the systematized method of the present invention, all the input elements are initialized to obtain a matrix. Based on the symmetry of the matrix and the similarity between the rows of the matrix are sequentially formed different sets respectively corresponding to the horizontally-continuous elements having the maximum iteration number in the horizontal and vertical directions, the symmetric non-continuous non-boundary elements, and the boundary elements plus the end-around neighboring elements in the same row. The present invention applies to any input number. Via the large intersection between the compared sets, the present invention can effectively reduce the number of comparison calculations and greatly promote the performance of an LDPC decoder.

Abstract: A frame-based phase-locked display controller used in a display system and method thereof are described. The frame-based phase-locked display controller for displaying a plurality of image frames in a video signal comprises a frame-based phase-locked loop and a synchronization signal generator. The frame-based phase-locked loop receives an oscillating signal and an input vertical synchronous signal to generate an output clock signal by phase-lock loop based on the frames. The synchronization signal generator, coupled to the frame-based phase-locked loop, receives the output clock signal to generate an output horizontal synchronous signal, an output vertical synchronous signal and an output display enable (DE) signal. The frame-based phase-locked loop comprises a first PLL, a frequency synthesizer, a second PLL, a fast phase detector, a phase frequency detector and an active pixel region generator.

Abstract: The present invention discloses a set-cyclic comparison method for an LDPC (Low-Density Parity-Check) decoder, which applies to a CNU (Check Node Unit) or a VNU (Variable Node Unit). In the systematized method of the present invention, all the input elements are initialized to obtain a matrix. Based on the symmetry of the matrix and the similarity between the rows of the matrix are sequentially formed different sets respectively corresponding to the horizontally-continuous elements having the maximum iteration number in the horizontal and vertical directions, the symmetric non-continuous non-boundary elements, and the boundary elements plus the end-around neighboring elements in the same row. The present invention applies to any input number. Via the large intersection between the compared sets, the present invention can effectively reduce the number of comparison calculations and greatly promote the performance of an LDPC decoder.

Abstract: The present invention discloses a cyclic comparison method for an LDPC decoder, which applies to the comparators used in an LDPC decoder. According to the cyclic comparison algorithm of the present invention, the nth element of the input k elements, wherein n=1, . . . , k, is sequentially removed by the corresponding comparator to obtain k first series. Next, pairs of two elements selected from the k elements are used to form k second series. The preceding step is repeated k×log2(k?1) times to obtain k completion series. Either of one first series and one completion series contains (k?1) elements. The first series are compared with the completion series to determine whether they are identical. If they are identical, the process stops. If they are not identical, the abovementioned step is repeated to obtain new completion series. The cyclic comparison method of the present invention needs only k×log2(k?1) comparisons to obtain completion series.

Abstract: A control device is used with a delta panel of a display for processing and transmitting color data to be displayed on the delta panel according to a pixel clock received from the image processing circuit. A clock duplicating circuit of the control device processes said pixel clock into three clocks with respective frequency smaller than the frequency of the pixel clock. A clock adjusting device of the control device is coupled to the clock-duplicating circuit for processing the resulting three color clocks into a first color clock, a second color clock having a first phase difference from said first color clock, and a third color clock having a second phase difference from said second color clock, wherein the first color clock, the second color clock and the third color clock are output to the delta panel for sampling a first color data, a second color data and a third color data to the delta panel, respectively.

Abstract: A data-playing controller includes a register for storing a plurality of control parameters, a first-in-first-out buffer (FIFO) for storing data, and a control circuit capable of accessing a memory dynamically. The register can be electrically connected to a data-playing device. The control circuit can store the control parameters via the FIFO to the memory first, and then transfer the control parameters stored in the memory via the FIFO to the register during a synchronizing blank period.

Abstract: A frame-based phase-locked display controller used in a display system and method thereof are described. The frame-based phase-locked display controller for displaying a plurality of image frames in a video signal comprises a frame-based phase-locked loop and a synchronization signal generator. The frame-based phase-locked loop receives an oscillating signal and an input vertical synchronous signal to generate an output clock signal by phase-lock loop based on the frames. The synchronization signal generator, coupled to the frame-based phase-locked loop, receives the output clock signal to generate an output horizontal synchronous signal, an output vertical synchronous signal and an output display enable (DE) signal. The frame-based phase-locked loop comprises a first PLL, a frequency synthesizer, a second PLL, a fast phase detector, a phase frequency detector and an active pixel region generator.

Abstract: A data-playing controller includes a register for storing a plurality of control parameters, a first-in-first-out buffer (FIFO) for storing data, and a control circuit capable of accessing a memory dynamically. The register can be electrically connected to a data-playing device. The control circuit can store the control parameters via the FIFO to the memory first, and then transfer the control parameters stored in the memory via the FIFO to the register during a synchronizing blank period.

Abstract: A detecting device for correct endotracheal intubation includes a tube to be engaged into a trachea of a patient, a signal emitting device for engaging into the trachea of the patient and for emitting a signal, and a sensor for sensing the signal from the signal emitting device to detect the correct engagement of the tube in the trachea of the patient. The signal emitting device may be attached to the tube for engaging into the trachea together with the tube. A control device may treat the signal and may indicate the correct engagement of the tube in the trachea.