Abstract: A semiconductor device having a metal gate includes a substrate having a first gate trench and a second gate trench formed thereon, a gate dielectric layer respectively formed in the first gate trench and the second gate trench, a first work function metal layer formed on the gate dielectric layer in the first gate trench and the second gate trench, a second work function metal layer respectively formed in the first gate trench and the second gate trench, and a filling metal layer formed on the second work function metal layer. An opening width of the second gate trench is larger than an opening width of the first gate trench. An upper area of the second work function metal layer in the first gate trench is wider than a lower area of the second work function metal layer in the first gate trench.

Abstract: A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.

Abstract: A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.

Abstract: The present invention provides a method of manufacturing semiconductor device having metal gate. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench and then a first metal layer and a first material layer are formed in the first trench. Next, the first metal layer and the first material layer are flattened. The second sacrifice gate is removed to form a second trench and then a second metal layer and a second material layer are formed in the second trench. Lastly, the second metal layer and the second material layer are flattened.

Abstract: A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.

Abstract: A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.

Abstract: The present invention provides a structure of a resistor comprising: a substrate having an interfacial layer thereon; a resistor trench formed in the interfacial layer; at least a work function metal layer covering the surface of the resistor trench; at least two metal bulks located at two ends of the resistor trench and adjacent to the work function metal layer; and a filler formed between the two metal bulks inside the resistor trench, wherein the metal bulks are direct in contact with the filler.

Abstract: A manufacturing method of a semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench, forming a first work function metal layer in the first gate trench, forming a second work function metal layer in the first gate trench and the second gate trench, forming a first patterned mask layer exposing portions of the second work function metal layer in the first gate trench and the second gate trench, and performing an etching process to remove the exposed second work function metal layer.

Abstract: A metal gate process includes the following steps. An isolating layer on a substrate is provided, where the isolating layer has a first recess and a second recess. A first metal layer covering the first recess and the second recess is formed. A material is filled in the first recess but exposing a top part of the first recess. The first metal layer in the top part of the first recess and in the second recess is simultaneously removed. The material is removed. A second metal layer and a metal gate layer in the first recess and the second recess are sequentially filled.

Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.

Abstract: A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O2 ambience treatment is performed on at least one layer of the multi-layered stack structure. A conductive layer is formed on the multi-layered stack structure.

Abstract: The present invention provides a method of manufacturing semiconductor device having metal gates. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench. Then, a first metal layer is formed in the first trench. The second sacrifice gate is removed to form a second trench. Next, a second metal layer is formed in the first trench and the second trench. Lastly, a third metal layer is formed on the second metal layer wherein the third metal layer is filled into the first trench and the second trench.

Abstract: A SiC region and a source/drain region are formed such that the SiC region includes a first portion overlapping the source/drain region and a second portion protruding from the source/drain region to a position beneath the LDD region. The concentration of crystalline SiC in the second portion is higher than the concentration of crystalline SiC in the first portion. The SiC region may be formed through a normal implantation before the second spacer is formed, or the SiC region may be formed through a tilt implantation or deposition epitaxially in a recess having a sigma-shape like sidewall after the second spacer is formed.

Abstract: The present invention provides a method of manufacturing semiconductor device having metal gate. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench and then a first metal layer and a first material layer are formed in the first trench. Next, the first metal layer and the first material layer are flattened. The second sacrifice gate is removed to form a second trench and then a second metal layer and a second material layer are formed in the second trench. Lastly, the second metal layer and the second material layer are flattened.

Abstract: A SiC region and a source/drain region are formed such that the SiC region includes a first portion overlapping the source/drain region and a second portion protruding from the source/drain region to a position beneath the LDD region. The concentration of crystalline SiC in the second portion is higher than the concentration of crystalline SiC in the first portion. The SiC region may be formed through a normal implantation before the second spacer is formed, or the SiC region may be formed through a tilt implantation or deposition epitaxially in a recess having a sigma-shape like sidewall after the second spacer is formed.

Abstract: A transflective liquid crystal display device includes a first and a second substrates, a liquid crystal layer, and a plurality of reflective electrodes and transparent electrodes. The liquid crystal layer is interposed between the first and the second substrates and functions in an OCB mode. The reflective electrode and the transparent electrode in one picture element are spaced apart from each other to produce a transverse electric field when a voltage is applied across the liquid crystal layer.

Abstract: An optically compensated bend (OCB) liquid crystal display (LCD) panel is provided. The OCB LCD panel includes an active device array substrate, an opposite substrate, an OCB liquid crystal layer and a first patterned dielectric layer. The opposite substrate is disposed opposite to the active device array substrate, while the OCB liquid crystal layer is disposed between the active device array substrate and the opposite substrate. Besides, the first patterned dielectric layer is disposed on the active device array substrate. It is noted that the first patterned insulator has at least a first concave and at least a first transition surface corresponding thereto, such that an arrangement of the liquid crystal molecules of the OCB liquid crystal layer above the first transition surface is a hybrid state. In the above-mentioned OCB LCD panel, the OCB liquid crystal layer can be transited from a splay state to a bend state rapidly.

Abstract: A liquid crystal display (LCD) panel including a first substrate, a second substrate and a liquid crystal layer is provided. The first substrate includes a signal line, an insulating layer and a pixel electrode. The insulating layer is disposed between the signal line and the pixel electrode. The pixel electrode partly overlaps the signal line. The second substrate is parallel to the first substrate. The liquid crystal layer is disposed between the first substrate and the second substrate. When a cross-voltage is applied to the signal line and the pixel electrode, a fringe vertical field having different directions is formed on the peripheral of the partly overlapped area between the signal line and the pixel electrode, such that the liquid crystal layer produces at least one transition nucleus area according to the fringe vertical field.

Abstract: Two phase retardation compensation films with upper and lower slow axes being orthogonal to each other are used to clip a liquid crystal (LC) cell in a transflective liquid crystal display. In an orthogonal polarizer system, the axial difference between the slow axes of the retardation films and the LC molecules director in the LC cell is used to obtain the most suitable phase difference. The ON and OFF of the LC voltage are used to achieve the display function at the darkest state and the brightest state, so as to achieve a transmissive optical mode having low dispersion, wide viewing angle, and ultra-low dark state, without damaging the reflective mode.

Abstract: A method for showing various color temperatures on a digital display simultaneously, which is more convenient and reduces the time users spend tuning color temperatures according to the different color temperatures shown in a video frame.