Abstract: A semiconductor chip includes an active inner circuit; a die seal ring surrounding the active inner circuit; a first circuit structure fabricated at a first corner of the semiconductor chip outside the die seal ring and electrically connected to the die seal, wherein the first circuit structure has a first solder pad; and a second circuit structure fabricated at a second corner of the semiconductor chip outside the die seal ring and electrically connected to the die seal, wherein the second circuit structure has a second solder pad.

Abstract: A semiconductor wafer includes a plurality of active circuit die areas, each of which being bordered by a dicing line region through which the plurality of active circuit die areas are separated from each other, wherein each of the plurality of active circuit die areas has substantially four corners. An overcoat is deposited to cover both the active circuit die areas and the dicing line region. A first trench is formed by etching through the overcoat and disposed merely around the four corners of each active circuit die area. A reinforcing second trench is etched into the overcoat and is disposed in proximity to the first trench. A die seal ring is disposed in between the active circuit chip area and the first trench.

Abstract: A semiconductor wafer includes a plurality of active circuit die areas, each of which being bordered by a dicing line region through which the plurality of active circuit die areas are separated from each other by mechanical wafer dicing. Each of the plurality of active circuit die areas has four sides. An overcoat covers both the active circuit die areas and the dicing line region. An inter-layer dielectric layer is disposed underneath the overcoat. A reinforcement structure includes a plurality of holes formed within the dicing line region. The plurality of holes are formed by etching through the overcoat into the inter-layer dielectric layer and are disposed along the four sides of each active circuit die area. A die seal ring is disposed in between the active circuit chip area and the reinforcement structure.

Abstract: A parasitic capacitance-preventing dummy solder bump structure on a substrate has at least one conductive layer formed on the substrate, a dielectric layer employed to cover the conductive layer, an under bump metallurgy layer (UBM layer) formed on the dielectric layer, and a solder bump formed on the UBM layer.

Abstract: A wafer scribe line structure is provided. A plurality of lump patterns is set up to fill the entire scribe line area so that the amount of stress the wafer is subjected to during a dicing process is reduced, thereby reducing the probability of having a delamination at the interface of wafer layers. Moreover, the lump patterns can be formed simultaneously with metal interconnects in a metal interconnect process.

Abstract: A parasitic capacitance-preventing dummy solder bump structure on a substrate has at least one conductive layer formed on the substrate, a dielectric layer employed to cover the conductive layer, an under bump metallurgy layer (UBM layer) formed on the dielectric layer, and a solder bump formed on the UBM layer.

Abstract: A structure of solder bumps with improved coplanarility, comprising a substrate, a passivation layer, a plurality of Under Ball Metallurgy (UBM) layers and a plurality of solder bumps. The substrate has at least an active surface, and a plurality of bonding pads are provided thereon. The UBM layers with various areas are electrically connected to the bonding pads. Finally, the solder bumps are formed with uniform-height on the UBM layers. A method of forming solder bumps with improved coplanarity. A UBM structure with various sizes of openings is provided to control the volume of the solder, wherein the various sizes of openings are corresponding to the current distribution across the wafer. The purpose of the various openings is to control the volume of the solder in order to form uniform-heights of solder bumps, the coplanarity of the solder bumps can thus be improved.

Abstract: A method is proposed for forming solder areas over a lead frame through deposition of an oxidation layer rather than selective removal of a polyimide-made solder mask, which allows the fabrication of the lead frame to be carried out in a more cost-effective and advantageous manner. The method allows the fabrication of the lead frame to be carried out through stamping without etching. Moreover, it can make the overall integrated circuit package less easily subjected to cracking and more securely assembled. Still moreover, it can make the overall integrated circuit package less likely to be weakened in structural strength by moisture. This method is therefore more advantageous to use than the prior art.

Abstract: A semiconductor device and a manufacturing process thereof are proposed. With no use of a substrate or leads, the foregoing semiconductor device has a chip with its surfaces being exposed to the outside of the device, allowing the overall thickness of the device to be significantly minimized, and the heat-dissipating efficiency to be greatly improved, as well as the manufacturing process and cost to be simplified and reduced respectively. Moreover, unlike a conventional semiconductor device, the semiconductor device is manufactured without using a specific mold with protrusions, a drill or a laser beam, so that the manufacturing cost is further reduced, and crack in the encapsulant as well as flash during molding are prevented.

Abstract: A solder-pump fabrication method is proposed, which is used for the fabrication of solder bumps with high coplanarity over a semiconductor chip for flip-chip application. The proposed solder-bump fabrication method is characterized in the use of a two-step solder-bump fabrication process, including a first step of electroplating solder over UBM (Under Bump Metallization) pads to a controlled height still below the topmost surface of the mask, and a second step of screen-printing solder paste over the electroplated solder layer. The combined structure of the electroplated solder layer and the printed solder layer is then reflowed to form the desired solder bump. Since the proposed solder-bump fabrication method allows the solder material electroplated and printed over the UBM pads to be confined within the mask openings and never exceed the topmost surface of the mask, the resulted solder bumps would not be bridged to neighboring ones.

Abstract: A structure of solder bumps with improved coplanarility, comprising a substrate, a passivation layer, a plurality of Under Ball Metallurgy (UBM) layers and a plurality of solder bumps. The substrate has at least an active surface, and a plurality of bonding pads are provided thereon. The UBM layers with various areas are electrically connected to the bonding pads. Finally, the solder bumps are formed with uniform-height on the UBM layers. A method of forming solder bumps with improved coplanarity. A UBM structure with various sizes of openings is provided to control the volume of the solder, wherein the various sizes of openings are corresponding to the current distribution across the wafer. The purpose of the various openings is to control the volume of the solder in order to form uniform-heights of solder bumps, the coplanarity of the solder bumps can thus be improved.

Abstract: A method of fabricating a BGA (Ball Grid Array) IC package of the type having an encapsulating body is proposed, which allows the BGA IC package to be manufactured without having to use conventional organic substrate and encapsulating-body mold having cavity, so that the manufacture process can be more cost-effective to carry out than the prior art. The proposed method is characterized in the use of a copper piece which is selectively removed to form an encapsulating-body cavity for the forming of an encapsulating body therein. The proposed method requires no use of mold with cavity for the forming of the encapsulating body, allowing the same mold to be used for the fabrication of various BGA IC packages of different sizes.

Abstract: A multi-chip IC package for central pad chips is proposed, which can be used to pack one peripheral-pad IC chip and at least one central-pad IC chip therein. The multi-chip IC package includes a specially-designed lead frame having a central die pad and a lead portion separated from the central die pad by a gap. The central-pad IC chip is partly attached to the lead portion of the lead frame and partly attached to the central die pad of the lead frame such that the central pads on the central-pad IC chip can be aligned with the gap of lead frame so as to allow bonding wires electrically connecting the central-pad IC chip with the lead portion of the lead frame to pass therethrough. The characterized package allows the bonding wires applied to the central-pad IC chip to be short in length so as to retain IC performance and save manufacture cost, making this multi-chip IC package structure more advantageous to use than the prior art.

Abstract: A heat-dissipating device is designed for use in an integrated circuit package for heat dissipation. The heat-dissipating device is a molded piece of a heat-conductive material, having an exterior side which is to be exposed to the outside of the integrated circuit package. The heat-dissipating device is characterized in the forming of a staircase-like cutaway part at the edge of the exterior side thereof, which is formed with a plurality of stepped surfaces. During the molding process, the staircase-like cutaway part can help slow down the flowing speed of the encapsulation resin flow, so that the resin flow would hardly flash onto the exterior side of the heat-conductive device. In addition, the staircase-like form of the cutaway part provides a lengthier path that would hardly allow outside moisture to penetrate to the inside of the integrated circuit package and cause popcorn effect in the integrated circuit package. The manufactured integrated circuit package is therefore more reliable to use.