Abstract: An NFC (Near Field Communication) system is provided in the invention. The NFC system includes a power source, a capacitor, an NFC controller including an independent power domain, and a memory device disposed in the independent power domain. The capacitor is charged by the power source. The independent power domain of the NFC controller is supplied by the power source and/or the capacitor. The memory device is configured to maintain data. When the power source is removed therefrom or turned off, the independent power domain is supplied by the capacitor.

Abstract: A GNSS receiver and method for GNSS memory code generation are disclosed. The GNSS receiver comprises a buffer, a correlator, and a selector. The buffer receives and stores a plurality of first code segments. Each of the first code segment is at least a portion of a memory code. The selector selects a selecting window of the first code segments stored in the buffer as a second code segment according to the code phase selection signal. The correlator calculates a correlation between a received GNSS signal and the second code segment.

Abstract: A BOC signal acquisition and tracking apparatus and method. In the present invention, at least a BOC signal, a BOC-cos signal and a PRN coded signal are generated for a received signal. Depending on application condition (e.g. acquisition mode or tracking mode), autocorrelation of the BOC signal is combined with cross-correlation of the BOC signal and one of the BOC-cos signal and the PRN coded signal to generate a proper combined correlation result.

Abstract: A variable length fast Fourier transform (FFT) system and a method for performing the FFT system in a global navigation satellite system (GNSS) signal acquisition and tracking, which includes a memory and a number of processing elements are disclosed. Based on the GNSS signal tracking, the variable length FFT system performs a first FFT operation together with a first data length. Based on the GNSS signal acquisition, the variable length FFT system is divided into several FFT subsystems to simultaneously perform different operations with various data lengths different from the first data length. Thus, the variable length FFT system can enhance the hardware utility and increase throughputs.

Abstract: A computer system has a central processing unit, a north bridge electrically connected to the central processing unit, memory electrically connected to the north bridge, a south bridge electrically connected to the north bridge, and a peripheral device electrically connected to the south bridge. The south bridge includes a register for storings a plurality of pre-fetched read data to provide the pre-fetched read data to the peripheral device. The north bridge has an address queue module for storing an address of the pre-fetched read data, and a snooping module for checking whether a data value corresponding to the address is updated by the CPU. The north bridge assists the south bridge in obtaining and maintaining the pre-fetched read data for high efficiency and accuracy of read caching of the south bridge.

Abstract: A wireless device includes at least a transmitter to transmit a transmitting signal; a triggering device arranged to monitor an operating status of the wireless device when the transmitter is transmitting the transmitting signal; and a controller arranged to control the transmitter to adjust a throughput of the transmitting signal when the operating status is determined to satisfy a predetermined criterion.

Abstract: A shared memory device for a receiver system is disclosed. The receiver system is configured to have a first functional stage and a second functional stage for processing information carried by signals transmitted from a first transmitter system through a first carrier frequency and a second transmitter system through a second carrier frequency respectively. The shared memory device has a memory space, allocated to be commonly shared by the first functional stage and the second functional stage, for buffering processing data generated from the first functional stage or the second functional stage.

Abstract: A GNSS receiver and method for GNSS memory code generation are disclosed. The GNSS receiver comprises a buffer, a correlator, and a selector. The buffer receives and stores a plurality of first code segments. Each of the first code segment is at least a portion of a memory code. The selector selects a selecting window of the first code segments stored in the buffer as a second code segment according to the code phase selection signal. The correlator calculates a correlation between a received GNSS signal and the second code segment.

Abstract: An adaptive time-division multiplexing receiver and method for a GNSS system using pilot and data channels for each satellite are disclosed. According to the present invention, multiplexing hypotheses of correlation are properly distributed to pilot and data channels. The pilot and data channels of one satellite can be dealt with as two satellites. Alternatively, correlation is mainly executed to the pilot channel. After the pilot channel is acquired, information such as code phase and Doppler frequency of the satellite are known. Therefore, the data can be demodulated based on the known information.

Abstract: The invention provides a Global Navigation Satellite System (GNSS) receiver. In one embodiment, the GNSS receiver comprises a memory, a buffer, a correlator, and a selector. The memory stores a memory code and outputs a portion of the memory code as a first code segment. The buffer comprises a plurality of component buffers and stores the first code segment into one of the component buffers in order. The selector selects a portion of the first code segments stored in the buffer as a second code segment output to the correlator according to the code phase selection signal, wherein the data length of the second code segment is equal to a correlation data length of the correlator. The correlator calculates a correlation between a received GNSS signal with the correlation data length and the second code segment.

Abstract: A shared memory device for a receiver system is disclosed. The receiver system is configured to have a first functional stage and a second functional stage for processing information carried by signals from a first transmitter system and a second transmitter system respectively. The shared memory device has a memory space, allocated to be commonly shared by the first functional stage and the second functional stage, for buffering processing data generated from the first functional stage or the second functional stage.

Abstract: A multi-chip module (MCM) includes a first die and a second die. The first die supports a plurality of predetermined functions. The second die is coupled to the first die and comprises at least an option pad configured for a bonding option. The first die performs a predetermined function according to a bonding status of the option pad of the second die.

Abstract: For saving power of a central processing unit at a C3 power level upon processing a bus master request from a peripheral device, an arbitrator is disabled from transmitting any request to the central processing unit at the C3 power level. Afterwards, in response to a bus master request, the central processing unit is switched from the C3power level to a transitional C0 power level while keeping the arbitrator disabled, and then switched from the transitional C0 power level to a C2 power level while enabling the arbitrator to process the bus master request.

Abstract: A method for power management of a CPU and a system thereof, which drive the CPU to enter a more efficient power saving state are disclosed. A chip of the present invention sends a first control signal to drive the CPU to wake from a non-snooping sleep state and enter a normally executing instruction state as well as a system management mode to execute a system management interrupt routine. Then the chip enables an arbiter to transmit a bus master request to the CPU for processing. After completing the processing of the bus master request, the chip disables the arbiter and the CPU drives the chip to send a second control signal to drive the CPU to return to the non-snooping sleep state according the system management interrupt routine.

Abstract: A BOC signal acquisition and tracking apparatus and method. In the present invention, at least a BOC signal, a BOC-cos signal and a PRN coded signal are generated for a received signal. Depending on application condition (e.g. acquisition mode or tracking mode), autocorrelation of the BOC signal is combined with cross-correlation of the BOC signal and one of the BOC-cos signal and the PRN coded signal to generate a proper combined correlation result.

Abstract: A method of direct RF digitization for multiple RF signal bands such GNSS or wireless communication signal bands and a receiver using the method. By using the method, an optimal sampling frequency to be used in direct RF digitization for signals of multiple RF signal bands can be easily obtained. According to the present invention, one or more of the RF signal bands are selected to be shifted to target band(s). By doing so, the optimal sampling frequency can be easily calculated. Then the obtained sampling frequency is used in executing the direct RF digitization.

Abstract: A fraction chip correlation device for a spread spectrum receiver for receiving signals modulated with spread spectrum codes and a method for operating fractional chip correlation to spread spectrum signals received by the spread spectrum receiver are disclosed. In the present invention, at least one delayed version of an input signal is generated to be correlated with a local code replica to accomplish fractional chip correlation. By doing so, correlators can operate at a low speed, so that power consumption of the receiver can be significantly reduced.

Abstract: A BOC signal acquisition and tracking apparatus and method. In the present invention, a BOC subcarrier, a QBOC subcarrier and harmonics thereof are used as subcarriers. Those subcarriers can be mixed with a received signal and integration result of each mixing result is calculated. Then, all the integration results are combined as a combined correlation. Alternatively, those subcarriers can be combined as a synthesized subcarrier. The synthesized subcarrier is mixed with the received signal, and the integration of the mixing result is calculated to obtain a synthesized correlation.

Abstract: A multi-chip module (MCM) includes a first die and a second die. The first die supports a plurality of predetermined functions. The second die is coupled to the first die and comprises at least an option pad configured for a bonding option. The first die performs a predetermined function according to a bonding status of the option pad of the second die.

Abstract: The invention provides a Global Navigation Satellite System (GNSS) receiver. In one embodiment, the GNSS receiver comprises a memory, a buffer, a correlator, and a selector. The memory stores a memory code and outputs a portion of the memory code as a first code segment. The buffer comprises a plurality of component buffers and stores the first code segment into one of the component buffers in order. The selector selects a portion of the first code segments stored in the buffer as a second code segment output to the correlator according to the code phase selection signal, wherein the data length of the second code segment is equal to a correlation data length of the correlator. The correlator calculates a correlation between a received GNSS signal with the correlation data length and the second code segment.