Abstract: A post correlation system for a GNSS receiver uses an FFT engine to perform post-FFT operation to obtain spectrum data. The system has a contender selector for sieving magnitude results of the spectrum data meeting some specific conditions for selected hypotheses. The sieved magnitudes results rather than all the magnitude results are stored into a memory. By doing so, the requirement of the memory capacity can be significantly reduced.

Abstract: A correlation system for a GNSS receiver uses an FFT engine to perform correlation and post-FFT operation. The FFT engine executes FFT operation to an input data stream so as to generate a frequency-domain correlation with frequency-domain C/A code and IFFT operation to the frequency-domain correlation result to generate post correlation data for each hypothesis, and executes FFT operation to the post correlation data of a selected hypothesis to generate a post-correlation FFT result in a programmable TDM manner. In the present invention, in addition to the FFT engine, some components such as a magnitude calculation unit and memory are shared by a correlation stage and a post-correlation stage. Therefore, hardware complexity can be reduced.

Abstract: The present invention discloses a variable length fast Fourier transform (FFT) system and a method for performing the FFT system in a global navigation satellite system (GNSS) signal acquisition and tracking, which includes a memory and a number of processing elements. Based on the GNSS signal tracking, the variable length FFT system performs a first FFT operation together with a first data length. Based on the GNSS signal acquisition, the variable length FET system is divided into several FFT subsystems to simultaneously perform different operations with various data lengths different from the first data length. Thus, the variable length FFT system can enhance the hardware utility and increase throughputs.

Abstract: A method for a power management of a central processor unit is disclosed. The method is applied to when the central processor unit is in a low power state without snooping and a bus master signal is sent from a peripheral device. First, a South Bridge sends a control signal to a central processor unit to drive the central processor unit to enter a low power state allowing snooping. Afterward an arbiter of the North Bridge is enabled. If the bus master signal is sent from the peripheral device to the South Bridge, an arbiter of the South Bridge is also enabled. And then the bus master signal is snooped by the central processor unit and the data is transmitted. After the bus master signal is snooped and the data has been transmitted, the arbiters are disabled and the South Bridge drives the central processor unit to return to the low power state without snooping.

Abstract: The invention provides a correlation device performing correlation on a received Global Navigation Satellite System (GNSS) signal. The correlation device comprises a first decimation module, a second decimation module, and a correlation module. The first decimation module decimates a plurality of samples of the received GNSS signal to obtain a plurality of decimated samples. The second decimation module decimates a plurality of code bits of a locally generated replica code to obtain a plurality of decimated code bits. The correlation module correlates the decimated samples with the decimated code bits to obtain a plurality of correlation results, thus achieving a coarse correlation between the received GNSS signal and the locally generated replica code.

Abstract: A BOC signal acquisition and tracking apparatus and method. In the present invention, at least a BOC signal, a BOC-cos signal and a PRN coded signal are generated for a received signal. Depending on application condition (e.g. acquisition mode or tracking mode), autocorrelation of the BOC signal is combined with cross-correlation of the BOC signal and one of the BOC-cos signal and the PRN coded signal to generate a proper combined correlation result.

Abstract: A fraction chip correlation device for a spread spectrum receiver for receiving signals modulated with spread spectrum codes and a method for operating fractional chip correlation to spread spectrum signals received by the spread spectrum receiver are disclosed. In the present invention, at least one delayed version of an input signal is generated to be correlated with a local code replica to accomplish fractional chip correlation. By doing so, correlators can operate at a low speed, so that power consumption of the receiver can be significantly reduced.

Abstract: An adaptive time-division multiplexing receiver and method for a GNSS system using pilot and data channels for each satellite are disclosed. According to the present invention, multiplexing hypotheses of correlation are properly distributed to pilot and data channels. The pilot and data channels of one satellite can be dealt with as two satellites. Alternatively, correlation is mainly executed to the pilot channel. After the pilot channel is acquired, information such as code phase and Doppler frequency of the satellite are known. Therefore, the data can be demodulated based on the known information.

Abstract: A bus controller and a control method are used in a computer system. In a bus controller, a bus controller main circuit issues a first signal to the central processing unit in response to a bus configuration cycle for indicating the presence of a first-level bus that the first group of components is coupled to. A virtual bridge device issues a second signal to the central processing unit in response to the bus configuration cycle for indicating the presence of a second-level bus that the second group of components is coupled to. A path selection unit electrically connected to the first and second groups of components via the first-level and second-level buses, respectively, outputs a normal device select signal to one of the first-level and second-level buses while outputting an invalid device select signal to the other of the first-level and second-level buses according to address data of a transaction.

Abstract: A shared memory device for a receiver system is disclosed. The receiver system is configured to have a first functional stage and a second functional stage for processing information carried by signals from a first transmitter system and a second transmitter system respectively. The shared memory device has a memory space, allocated to be commonly shared by the first functional stage and the second functional stage, for buffering processing data generated from the first functional stage or the second functional stage.

Abstract: A BOC signal acquisition and tracking apparatus and method. In the present invention, a BOC subcarrier, a QBOC subcarrier and harmonics thereof are used as subcarriers. Those subcarriers can be mixed with a received signal and integration result of each mixing result is calculated. Then, all the integration results are combined as a combined correlation. Alternatively, those subcarriers can be combined as a synthesized subcarrier. The synthesized subcarrier is mixed with the received signal, and the integration of the mixing result is calculated to obtain a synthesized correlation.

Abstract: A programmable direct RF digitization receiver for multiple RF signal bands such as GNSS bands and other wireless communication bands. The receiver has a programmable frequency provision unit. The programmable frequency provision unit provides a shared sampling frequency or respective sampling frequencies based on selected bands so that the receiver can executes digitization to down-convert received signals of the selected bands with the sampling frequency or frequencies. By using the receiver of the present invention, different band combinations can be supported with great flexibility. In addition performance such as SNR (signal-to-noise ratio) can be fine tuned by adjusting the separation of down-converted IF bands.

Abstract: A method of direct RF digitization for multiple RF signal bands such GNSS or wireless communication signal bands and a receiver using the method. By using the method, an optimal sampling frequency to be used in direct RF digitization for signals of multiple RF signal bands can be easily obtained. According to the present invention, one or more of the RF signal bands are selected to be shifted to target band(s). By doing so, the optimal sampling frequency can be easily calculated. Then the obtained sampling frequency is used in executing the direct RF digitization.

Abstract: For saving power of a central processing unit at a C3 power level upon processing a bus master request from a peripheral device, an arbitrator is disabled from transmitting any request to the central processing unit at the C3 power level. Afterwards, in response to a bus master request, the central processing unit is switched from the C3 power level to a transitional C0 power level while keeping the arbitrator disabled, and then switched from the transitional C0 power level to a C2 power level while enabling the arbitrator to process the bus master request.

Abstract: A connected indicator wire of open-drained configuration is set between a north bridge and a south bridge. When either the south or north bridge is handling a bus master request, a bus master indicator (BMI) signal is asserted to the connected indicator wire. With open-drained configuration, the signal of the connected indicator wire is capable of reflecting whether a BMI signal is asserted, and accordingly, the south bridge controls the CPU to switch between power saving states for responding to the bus master request. The CPU does not have to resume a full-function power state to coordinate a bus master service.

Abstract: A method for power management of CPU and a system thereof which drive the CPU enter a most efficient power saving state is disclosed. A chip of the present invention sends a first control signal to drive the CPU to wake from the non-snooping sleep state and enter a normally executing instruction state as well as a system management mode to execute a system management interrupt routine. Then the chip enables an arbiter to transmit the bus master request to the CPU for processing. After completing processing the bus master request, the chip disables the arbiter and the CPU drives the chip sends a second control signal to drive the CPU return to the non-snooping sleep state according the system management interrupt routine.

Abstract: A method for facilitating read completion in a computer system supporting write posting operations. A posted memory write and its associated tag both need to be buffered, where the associated tag is designated to a master of a local bus originating the posted memory write. When a read request moving in an opposite direction of the posted memory write is detected, the read request is checked to identify which master of the local bus is addressed. A destination tag is then assigned to the read request contingent upon the currently addressed master. Further, the destination tag of the read request is compared with the associated tag of the posted memory write. If the destination tag of the read request differs from the associated tag of the posted memory write, the read request can be completed directly regardless of the outstanding posted writes.

Abstract: A method for a power management of a central processor unit is disclosed. The method is applied to when the central processor unit is in a low power state without snooping and a bus master signal is sent from a peripheral device. First, a South Bridge sends a control signal to a central processor unit to drive the central processor unit to enter a low power state allowing snooping. Afterward an arbiter of the North Bridge is enabled. If the bus master signal is sent from the peripheral device to the South Bridge, an arbiter of the South Bridge is also enabled. And then the bus master signal is snooped by the central processor unit and the data is transmitted. After the bus master signal is snooped and the data has been transmitted, the arbiters are disabled and the South Bridge drives the central processor unit to return to the low power state without snooping.

Abstract: A bus controller and a control method are used in a computer system. In a bus controller, a bus controller main circuit issues a first signal to the central processing unit in response to a bus configuration cycle for announcing a first-level bus that the first group of components is coupled to. A virtual bridge device issues a second signal to the central processing unit in response to the bus configuration cycle for announcing a second-level bus that the second group of components is coupled to. A path selection unit electrically connected to the first and second groups of components via the first-level and second-level buses, respectively, outputs a normal device select signal to one of the first-level and second-level buses while outputting an invalid device select signal to the other of the first-level and second-level buses according to address data of a transaction.

Abstract: A connected indicator wire of open-drained configuration is set between a north bridge and a south bridge. When either the south or north bridge is handling a bus master request, a bus master indicator (BMI) signal is asserted to the connected indicator wire. With open-drained configuration, the signal of the connected indicator wire is capable of reflecting whether a BMI signal is asserted, and accordingly, the south bridge controls the CPU to switch between power saving states for responding to the bus master request. The CPU does not have to resume a full-function power state to coordinate a bus master service.