Abstract: An electronic memory device includes a memory-cell circuit. The electronic memory device also includes a non-memory-cell circuit. The non-memory cell circuit includes an active region. The active region extends in a first direction in a top view. The active region includes a first segment and a second segment. The first segment has a first dimension measured in a second direction in the top view. The second segment has a second dimension measured in the second direction different from the first direction in the top view. The second dimension is different from the first dimension.

Abstract: A semiconductor structure according to the present disclosure includes a first memory array in a first cache and a second memory array in a second cache. The first memory array includes a plurality of first memory cells arranged in M1 rows and N1 columns. The second memory array includes a plurality of second memory cells arranged in M2 rows and N2 columns. The semiconductor structure also includes a first bit line coupled to a number of N1 first memory cells in one of the M1 rows, and a second bit line coupled to a number of N2 second memory cells in one of the M2 rows. N1 is smaller than N2, and a width of the first bit line is smaller than a width of the second bit line.

Abstract: A memory device is provided. The memory device includes a memory cell array having a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns. Each of the plurality of columns include a first plurality of memory cells connected to a first bit line and a second bit line. A pre-charge circuit is connected to the memory cell array. The pre-charge circuit pre-charges each of the first bit line and the second bit line from a first end. A pre-charge assist circuit is connected to the memory cell array. The pre-charge assist circuit pre-charges each of the first bit line and the second bit line from a second end, the second end being opposite the first end.

Abstract: A light-emitting module includes a light source module, a collimating lens module and a deflecting diffraction module. The light source module includes at least two light source arrays. Each light source arrays is configured to emit beams of detection light. The collimating lens module is on an output side of the light source module and includes a plurality of collimating lenses. The deflecting diffraction module is on a side of the collimating lens module facing away the light source module. The deflecting diffraction module is configured to superimpose groups of the detection light.

Abstract: A memory device is provided. The memory device includes a memory cell array having a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns. Each of the plurality of columns include a first plurality of memory cells connected to a first bit line and a second bit line. A pre-charge circuit is connected to the memory cell array. The pre-charge circuit pre-charges each of the first bit line and the second bit line from a first end. A pre-charge assist circuit is connected to the memory cell array. The pre-charge assist circuit pre-charges each of the first bit line and the second bit line from a second end, the second end being opposite the first end.

Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.

Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.

Abstract: A memory device includes a first pull-down (PD) transistor, a second PD transistor, a first pass-gate (PG) transistor, and a second PG transistor arranged in a first direction and share a first active area, and a first pull-up (PU) transistor, a second PU transistor, a first dielectric structure, and a second dielectric structure arranged in the first direction and share a second active area. The first dielectric structure and a third gate structure of the first PG transistor extend in the second direction and are aligned with each other in the second direction. The second dielectric structure and a fourth gate structure of the second PG transistor extend in the second direction and are aligned with each other in the second direction.

Abstract: A semiconductor device comprising a plurality of cells arranged in an array is disclosed. Each cell comprises: at least one active region arranged along a first direction; and at least five spaced apart conductive regions arranged along a second direction disposed over the active regions, wherein the first through fifth conductive regions comprise one or more conductors, wherein the one or more conductors have a dimension along the first direction. The dimension along the first direction is larger for at least one conductor in the first or fifth conductive regions than the dimension along the first direction for a conductor in the third conductive region. The pitch between conductors in the second and the fourth conductive region and the pitch between a conductor in the second or fourth conductive region and a conductor in a next closest conductive region that is not the second or fourth conductive region are different.

Abstract: A method includes providing a substrate having an epitaxial stack of layers including a plurality of semiconductor channel layers interposed by a plurality of dummy layers. The substrate includes a first device region and a second device region. An etch process is performed to remove a first portion of the epitaxial stack of layers from the second device region to form a trench in the second device region. The removed first portion of the epitaxial stack of layers includes at least one semiconductor channel layer of the plurality of semiconductor channel layers. An epitaxial layer is formed within the trench in the second device region and over the second portion of the epitaxial stack of layers. A top surface of the epitaxial layer in the second device region is substantially level with a top surface of the epitaxial stack of layers in the first device region.

Abstract: A memory device is provided. The memory device includes a memory cell array having a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns. Each of the plurality of columns include a first plurality of memory cells connected to a first bit line and a second bit line. A pre-charge circuit is connected to the memory cell array. The pre-charge circuit pre-charges each of the first bit line and the second bit line from a first end. A pre-charge assist circuit is connected to the memory cell array. The pre-charge assist circuit pre-charges each of the first bit line and the second bit line from a second end, the second end being opposite the first end.

Abstract: A performance management system, method and a non-transitory computer readable storage medium are disclosed herein. The performance management system includes a value-driven management module and an integrated control module. The value-driven management module includes a value-driven model configuration unit and a value-driven target configuration unit. The value-driven model configuration unit is configured to configure a value-driven model with a plurality of targets, and the targets respond to a plurality of factors. The value-driven target configuration unit is configured to set a goal value for each of the targets. The integrated control module is configured to monitor a performance of a building in accordance with the goal value for each of the targets and the value-driven model.

Abstract: A method for controlling temperatures in hot runners of a multi-cavity injection mold, a warning method, and a control system based on those methods are provided, in which a temperature sensor is positioned at the same location as each of the cavities of the mold, one of the cavities is chosen as a standard cavity, and a standard filling time is defined. Besides, in every injection cycle, a calculating and controlling module is to calculate the differences between the standard filling time and the filling times of the cavities, and according to the differences, the temperatures in the hot runners may be adjusted by a temperature-adjusting device and a warning device may be started. So, the volumetric filling of the cavities can be balanced very quickly, the process can avoid fluctuations of external environment so as to reduce the time for product development, and the quality of production can be maintained.

Abstract: A method for controlling temperatures in hot runners of a multi-cavity injection mold, a warning method, and a control system based on those methods are provided, in which a temperature sensor is positioned at the same location as each of the cavities of the mold, one of the cavities is chosen as a standard cavity, and a standard filling time is defined. Besides, in every injection cycle, a calculating and controlling module is to calculate the differences between the standard filling time and the filling times of the cavities, and according to the differences, the temperatures in the hot runners may be adjusted by a temperature-adjusting device and a warning device may be started. So, the volumetric filling of the cavities can be balanced very quickly, the process can avoid fluctuations of external environment so as to reduce the time for product development, and the quality of production can be maintained.