Patents by Inventor Jui-Yuan Tsai

Jui-Yuan Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190172978
    Abstract: A light emitting unit and a display device is disclosed, wherein the display device includes: a light emitting unit, including: a first semiconductor layer; an active layer disposed on the first semiconductor layer; a second semiconductor layer disposed on the active layer; and a first protecting layer disposed on the second semiconductor layer, wherein the first protecting layer includes oxygen, nitrogen, and at least one element selected from the group consisting of Al, Ga, In, and Si.
    Type: Application
    Filed: December 1, 2017
    Publication date: June 6, 2019
    Inventors: Jia-Yuan CHEN, Kuan-Feng LEE, Tsung-Han TSAI, Hsiao-Lang LIN, Jui-Jen YUEH
  • Patent number: 10312414
    Abstract: A light emitting unit and a display device is disclosed, wherein the display device includes: a light emitting unit, including: a first semiconductor layer; an active layer disposed on the first semiconductor layer; a second semiconductor layer disposed on the active layer; and a first protecting layer disposed on the second semiconductor layer, wherein the first protecting layer includes oxygen, nitrogen, and at least one element selected from the group consisting of Al, Ga, In, and Si.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: June 4, 2019
    Assignee: INNOLUX CORPORATION
    Inventors: Jia-Yuan Chen, Kuan-Feng Lee, Tsung-Han Tsai, Hsiao-Lang Lin, Jui-Jen Yueh
  • Publication number: 20190162992
    Abstract: A display device includes a first display unit and a second display unit. The first display unit emits a red light having a first output spectrum corresponding to a highest gray level of the display device. The second display unit emits a blue light having a second output spectrum corresponding to the highest gray level of the display device. Wherein, an intensity integral of the first output spectrum within a range from 380 nm to 780 nm is defined as a first intensity integral, an intensity integral of the second output spectrum within a range from 494 nm to 580 nm is defined as a second intensity integral, a ratio of the second intensity integral to the first intensity integral is defined as a first ratio, and the first ratio is greater than 0% and less than or equal to 28.0%.
    Type: Application
    Filed: January 31, 2019
    Publication date: May 30, 2019
    Inventors: Hsiao-Lang Lin, Jia-Yuan Chen, Jui-Jen Yueh, Kuan-Feng Lee, Tsung-Han Tsai
  • Patent number: 8446405
    Abstract: A DC level redistribution method includes the steps of: receiving all positive signals and one negative signal of a plurality of pairs of differential signals; fixing a DC level of a positive signal of a designated pair of differential signals among a plurality of pairs of differential signals as a reference in order to adjust a DC level of a negative signal of the designated pair of differential signals for generating an adjusted negative signal; and taking the adjusted negative signal of the designated pair of differential signals as a reference in order to adjust DC levels of the positive signals of the other pairs of differential signals excluding the designated pair of differential signals. The DC redistribution method may be used in a display system.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: May 21, 2013
    Assignee: Realtek Semiconductor Corp.
    Inventors: Szu-Ping Chen, Jui-Yuan Tsai, Cheng-Jui Chen
  • Publication number: 20120303295
    Abstract: The direction sensing apparatus according to the present invention comprises a sensing circuit, a computing module, and a judging unit. The sensing circuit detects the gravity direction of an object and produces at least a detecting signal. The computing module receives the detecting signal, and produces at least a computing value according to at least a threshold value and the detecting signal. The judging unit receives the computing value, and gives a state of gravity direction of the object according to the computing value. Thereby, the present invention shrinks the area of circuits and hence saving cost by means of the simple circuit structure of the computing module.
    Type: Application
    Filed: March 19, 2012
    Publication date: November 29, 2012
    Applicant: SITRONIX TECHNOLOGY CORP.
    Inventors: CHI-TIEN YEH, WEI-YANG OU, JUI-YUAN TSAI
  • Patent number: 8290065
    Abstract: The invention discloses an image processing system comprising a video source system, a transmission medium, and a television system. The image processing systems of the video source system and the television system are equipped with an additional digital-to-analog converter and an additional analog-to-digital converter.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: October 16, 2012
    Assignee: Realtek Semiconductor Corp.
    Inventors: Jui-Yuan Tsai, Chao-Hsin Lu
  • Patent number: 8284925
    Abstract: A jack detection circuit includes a transition circuit and an AD converter. The transition circuit linearizes analog signals sent from a switching circuit. The AD converter converts the linearized analog signals to digital output signals thereby decreasing the complexity of signal recognition.
    Type: Grant
    Filed: July 17, 2007
    Date of Patent: October 9, 2012
    Assignee: Realtek Semiconductor Corp.
    Inventors: Jui Yuan Tsai, Wen Chi Wang, Wei Cheng Tang
  • Patent number: 8212938
    Abstract: A sync signal acquisition device is disclosed which comprises a transistor, a resistor, a clamper, an analog multiplexer and a comparator. While operating in a composite HS mode, prior to the generation of the sync signal HS, the invention uses a conventional circuit to extract a composite sync signal at start-up, thereby allowing related circuits to generate the sync signal HS and a clamping signal. Then, a mode selecting signal is used to disable the automatic clamping mode and switch the analog multiplexer to a forced clamping mode. At this point, the output voltage of the damper is set by a user instead of process; accordingly, the DC voltage level is more controllable, but not subject to drift due to process changes or temperature changes.
    Type: Grant
    Filed: July 5, 2007
    Date of Patent: July 3, 2012
    Assignee: Realtek Semiconductor Corp.
    Inventors: Jui-Yuan Tsai, Szu-Ping Chen, Yu-Pin Chou
  • Patent number: 8184028
    Abstract: A video data source system includes a video encoder and an analog back end device. The analog back end device includes a digital to analog converter and a post-stage driving unit. The video data source system adds the post-stage driving unit into the analog back end device and strengthens its driving ability by the post-stage driving unit.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: May 22, 2012
    Assignee: Realtek Semiconductor Corp.
    Inventor: Jui-Yuan Tsai
  • Patent number: 8159609
    Abstract: The invention relates to an image processing chip and related method. The image processing chip includes a pin for receiving a composite signal; a synchronization signal detecting circuit, coupled to the pin, for extracting a synchronization signal from the composite signal; a clamping circuit, coupled to the pin, for adjusting a voltage level of the composite signal according to the synchronization signal; and an analog to digital converter, coupled to the pin, for generating a video signal by sampling the composite signal.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: April 17, 2012
    Assignee: Realtek Semiconductor Corp.
    Inventors: Jin-Sheng Gong, Jui-Yuan Tsai, Yu-Pin Chou, Yueh-Hsing Huang
  • Patent number: 8130422
    Abstract: An image processing device is provided which comprises an input unit and an analog front end circuit with DC inputs. According to the invention, no capacitor is installed in the input unit and no clamper is installed in the AFE circuit with DC inputs. By appropriately selecting a comparing voltage and adding a level shifter or a compensation circuit, the invention can still generate an accurate digital signal.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: March 6, 2012
    Assignee: Realtek Semiconductor Corp.
    Inventor: Jui-Yuan Tsai
  • Patent number: 7982701
    Abstract: An analog front end device with temperature compensation is provided. The analog front end device comprises a bandgap voltage reference circuit, a clock generator, a temperature compensation circuit, one to three identical converting circuits and a Sync-on-Green circuit. The temperature compensation circuit is adapted to sense the temperature variations of the analog front end device and dynamically compensate the bandgap voltage reference circuit, the clock generator and the Sync-on-Green circuit as the temperature varies, which thereby controls the thermal drift in the analog front end device.
    Type: Grant
    Filed: July 5, 2007
    Date of Patent: July 19, 2011
    Assignee: Realtek Semiconductor Corp.
    Inventors: Jui-Yuan Tsai, Szu-Ping Chen
  • Patent number: 7916062
    Abstract: An analog front-end processing apparatus capable of sharing pins includes a plurality of positive pins, a negative pin, a plurality of positive clamping circuits, a negative clamping circuit, a plurality of sample and hold circuits and a plurality of adjusting circuits. The positive clamping circuits have positive signals fixed at their corresponding target positive voltages. The negative clamping circuit has a negative signal fixed at a first reference voltage. Each sample and hold circuit has a positive input terminal and a negative input terminal, wherein a voltage difference between the two input terminals is substantially equal to a voltage difference between the corresponding target positive voltage and the first reference voltage during a sample period, and a voltage difference between the two input terminals is equal to a voltage difference between the corresponding target negative voltage and a second reference voltage during a hold period.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: March 29, 2011
    Assignee: Realtek Semiconductor Corp.
    Inventors: Jui-Yuan Tsai, Cheng-Jui Chen
  • Publication number: 20100066725
    Abstract: A DC level redistribution method includes the steps of: receiving all positive signals and one negative signal of a plurality of pairs of differential signals; fixing a DC level of a positive signal of a designated pair of differential signals among a plurality of pairs of differential signals as a reference in order to adjust a DC level of a negative signal of the designated pair of differential signals for generating an adjusted negative signal; and taking the adjusted negative signal of the designated pair of differential signals as a reference in order to adjust DC levels of the positive signals of the other pairs of differential signals excluding the designated pair of differential signals. The DC redistribution method may be used in a display system.
    Type: Application
    Filed: September 17, 2009
    Publication date: March 18, 2010
    Inventors: Szu-Ping Chen, Jui-Yuan Tsai, Cheng-Jui Chen
  • Publication number: 20100066428
    Abstract: An analog front-end processing apparatus capable of sharing pins includes a plurality of positive pins, a negative pin, a plurality of positive clamping circuits, a negative clamping circuit, a plurality of sample and hold circuits and a plurality of adjusting circuits. The positive clamping circuits have positive signals fixed at their corresponding target positive voltages. The negative clamping circuit has a negative signal fixed at a first reference voltage. Each sample and hold circuit has a positive input terminal and a negative input terminal, wherein a voltage difference between the two input terminals is substantially equal to a voltage difference between the corresponding target positive voltage and the first reference voltage during a sample period, and a voltage difference between the two input terminals is equal to a voltage difference between the corresponding target negative voltage and a second reference voltage during a hold period.
    Type: Application
    Filed: September 17, 2009
    Publication date: March 18, 2010
    Inventors: Jui-Yuan Tsai, Cheng-Jui Chen
  • Patent number: 7679541
    Abstract: A circuit and method for improving mismatches between signal converters includes at least two conversion units, a clock generator and a reference voltage generator. The conversion units share the clock generator and/or the reference voltage generator so as to improve mismatches between the conversion units.
    Type: Grant
    Filed: June 13, 2007
    Date of Patent: March 16, 2010
    Assignee: Realtek Semiconductor Corp.
    Inventor: Jui Yuan Tsai
  • Patent number: 7545299
    Abstract: The invention discloses an analog front end device includes a calibration unit and at least a conversion circuit. The conversion circuit includes a clamper, a multiplexer, an voltage buffer and an analog to digital converter. The clamper receives an image signal and resets the DC voltage level of the image signal to generate a clamped signal. The multiplexer receives the clamped signal and a test signal and outputs the clamped signal or the test signal according to a selecting signal. The voltage buffer amplifies the clamped signal or the test signal to generate a buffer signal. The analog to digital converter converts the buffer signal into a digital signal. The calibration unit generates a gain correction value according to the test signal and calibrates the gain offset of the digital signal according to the gain correction value.
    Type: Grant
    Filed: September 24, 2007
    Date of Patent: June 9, 2009
    Assignee: Realtek Semiconductor Corp.
    Inventors: Jui-Yuan Tsai, Chi-Kung Kuan
  • Patent number: 7525469
    Abstract: An image processing device is provided which includes a pseudo differential analog front end circuit for receiving at least one image analog signal and generating at least one digital signal. The pseudo differential analog front end circuit includes at least a converting circuit, each of which includes a clamper, an input buffer and an analog-to-digital converter. All of the analog-to-digital converters receive a common comparing voltage if the number of the converting circuits is greater than one.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: April 28, 2009
    Assignee: Realtek Semiconductor Corp.
    Inventor: Jui-Yuan Tsai
  • Patent number: 7456769
    Abstract: A reference voltage generating circuit includes a first capacitor having a first end and a second end; a second capacitor having a third end and a fourth end; a first switch for selectively coupling a predetermined voltage to the first end of the first capacitor; a second switch for selectively coupling the third end of the second capacitor to the first end of the first capacitor; a third switch for selectively coupling the first end of the first capacitor to a reference voltage level; and a fourth switch for selectively coupling the second end of the first capacitor to a reference voltage level; wherein the first capacitor samples the predetermined voltage in a first stage and re-distributes charges to the second capacitor in a second stage.
    Type: Grant
    Filed: July 24, 2006
    Date of Patent: November 25, 2008
    Assignee: Realtek Semiconductor Corp.
    Inventors: Wen-Chi Wang, Chang-Shun Liu, Chao-Cheng Lee, Jui-Yuan Tsai
  • Publication number: 20080084338
    Abstract: The invention discloses an analog front end device includes a calibration unit and at least a conversion circuit. The conversion circuit includes a clamper, a multiplexer, an voltage buffer and an analog to digital converter. The clamper receives an image signal and resets the DC voltage level of the image signal to generate a clamped signal. The multiplexer receives the clamped signal and a test signal and outputs the clamped signal or the test signal according to a selecting signal. The voltage buffer amplifies the clamped signal or the test signal to generate a buffer signal. The analog to digital converter converts the buffer signal into a digital signal. The calibration unit generates a gain correction value according to the test signal and calibrates the gain offset of the digital signal according to the gain correction value.
    Type: Application
    Filed: September 24, 2007
    Publication date: April 10, 2008
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Jui-Yuan Tsai, Chi-Kung Kuan