Abstract: An analog front-end (AFE) circuit of a digital display is disclosed including: a first analog-to-digital converter (ADC) for converting a first analog video signal into a first digital video signal according to a first sampling signal; a second ADC for converting the first analog video signal into a second digital video signal according to the first sampling signal; a first multiplexer for selectively outputting the first digital video signal or the second digital video signal according to a first output order; and a first clock control circuit for randomly adjusting the first output order of the first and the second digital video signals.

Abstract: An analog front-end (AFE) circuit of a digital display is disclosed including: a first circuit to intermittently invert a working clock to generate a control signal and to generate a sampling signal, wherein the sampling signal is corresponding to the working clock; a first analog-to-digital converter (ADC) coupled to the first circuit for converting an analog video signal into a first digital video signal according to the sampling signal; a second analog-to-digital converter coupled to the first circuit for converting the analog video signal into a second digital video signal according to the sampling signal; and a first multiplexer for selectively outputting the first digital video signal or the second digital video signal according to the control signal.

Abstract: A pipeline ADC has a plurality of analog-to-digital conversion units cascaded in series to form a pipeline. An error correcting method for the pipeline ADC includes during a first mode, measuring the plurality of analog-to-digital conversion units utilizing an extra analog-to-digital conversion module; calculating a plurality of correction constant sets according to digital output values of the extra analog-to-digital conversion module in the measuring step; and during a second mode, correcting output signals of the plurality of analog-to-digital conversion units according to the correction constant sets.

Abstract: The variable gain amplifier of the present invention includes at least an operation amplifier. By choosing one of output stages, a feedback resistor is selected and the gain of the variable gain amplifier is decided according to the resistance of the selected feedback resistor, as desired. By adjusting the gain of the variable gain amplifier, the received signals can be amplified or attenuated in accordance with design requirement. The variable gain amplifier can include a two-stage architecture, in which a first stage is used for coarse gain adjustment and a second stage is used for fine gain adjustment. The gain of the two-stage variable gain amplifier can be easily adjusted to a desired value.

Abstract: A pipeline ADC includes a pipeline structure having a plurality of analog-to-digital converting units cascaded in series; and a correcting unit coupled to the pipeline structure for correcting an output value of the pipeline structure according to a set of calibration constants. One of the analog-to-digital converting units contains a capacitor switching circuit. During error measurement of the pipeline ADC, the capacitor switching circuit switches to change capacitance allocation of the analog-to-digital converting unit so as to obtain the set of calibration constants.

Abstract: The line driver with active termination includes: a differential amplifier having an inverting output terminal, a non-inverting output terminal, an inverting input terminal, and a non-inverting input terminal; a first resistor unit coupled to the inverting input terminal; a impedance matching resistor unit coupled to the non-inverting output terminal; and a resistive feedback network, having a plurality of resistors in symmetric configuration. The resistive feedback network further includes: a second resistor unit coupled to the impedance matching resistor unit and the inverting input terminal; a third resistor unit coupled to the non-inverting output terminal and the inverting input terminal; a fourth resistor unit coupled to the impedance matching resistor unit and the inverting input terminal; and a fifth resistor unit coupled to the inverting output terminal and the inverting input terminal.

Abstract: An output stage structure includes first and second PMOS transistors and first and second NMOS transistors, wherein the MOS transistors are manufactured with a twin well process. The first PMOS transistor has a source coupled to a supply voltage (VDD), and a gate coupled to the first voltage. The second PMOS transistor has a source coupled to a drain of the first PMOS transistor, a gate coupled to the second voltage, and a drain coupled to an output pad. The first NMOS transistor has a drain coupled to the output pad, and a gate coupled to the third voltage. The second NMOS transistor has a drain coupled to source of the first NMOS transistor, a gate coupled to the fourth voltage, and a source coupled to ground.

Abstract: An apparatus for channel balancing of a multi-channel analog-to-digital converter of a digital image display comprises a red, a green and a blue analog-to-digital converter for respectively receiving a red, a green and a blue analog signal of an image signal wherein the analog-to-digital converters respectively sample the red, green and blue analog signals through a sampling clock signal and output a corresponding digital signal. A phase difference processing unit is used for estimating the phase differences among the digital signals and outputting corresponding time delay signals according to the phase differences. A clock delay compensation unit is used for receiving the time delay signals and respectively compensating the time delays of the sampling clock signals of the analog-to-digital converters according to the time delay signals, thereby decreasing the phase differences among the digital signals.

Abstract: A pipeline ADC for converting an analog input signal to a digital output signal includes: a plurality of analog-to-digital converting units cascading in series to form a pipeline including a plurality of digital output ends; a calculation unit coupled to the analog-to-digital converting units for generating a plurality of calibration parameters in a first mode according to signals at the digital output ends; and a calibration unit coupled to the calculation unit and the analog-to-digital converting units for calibrating signals at the digital output ends in a second mode according to the calibration parameters, so as to generate the digital output signal.

Abstract: A pipeline ADC has a plurality of analog-to-digital conversion units cascaded in series to form a pipeline. An error correcting method for the pipeline ADC includes during a first mode, measuring the plurality of analog-to-digital conversion units utilizing an extra analog-to-digital conversion module; calculating a plurality of correction constant sets according to digital output values of the extra analog-to-digital conversion module in the measuring step; and during a second mode, correcting output signals of the plurality of analog-to-digital conversion units according to the correction constant sets.

Abstract: A pipeline ADC includes a pipeline structure having a plurality of analog-to-digital converting units cascaded in series; and a correcting unit coupled to the pipeline structure for correcting an output value of the pipeline structure according to a set of calibration constants. One of the analog-to-digital converting units contains a capacitor switching circuit. During error measurement of the pipeline ADC, the capacitor switching circuit switches to change capacitance allocation of the analog-to-digital converting unit so as to obtain the set of calibration constants.

Abstract: The variable gain amplifier of the present invention includes at least an operation amplifier. By choosing one of output stages, a feedback resistor is selected and the gain of the variable gain amplifier is decided according to the resistance of the selected feedback resistor, as desired. By adjusting the gain of the variable gain amplifier, the received signals can be amplified or attenuated in accordance with design requirement. The variable gain amplifier can include a two-stage architecture, in which a first stage is used for coarse gain adjustment and a second stage is used for fine gain adjustment. The gain of the two-stage variable gain amplifier can be easily adjusted to a desired value.

Abstract: An AFE device with adjustable bandwidth filtering functions includes an input buffer and an ADC, and the adjustable bandwidth filtering functions may be integrated in the ADC or the input buffer. When they are integrated in the ADC, a capacitor and a switch module in the ADC may implement the functions, wherein the capacitor originally samples and holds analog signals. The switch module includes a plurality of transistor switches connected in parallel, and one (or multiple ones connected in parallel) of the transistor switches may be selected, according to a selection code, as an equivalent resistor to be serially connected to the capacitor to form a filter circuit. The selection code may be a one-of-N code or a thermometer code.

Abstract: An amplifier circuit having a high time constant. An operational amplifier includes a non-converting input terminal coupled to a ground, a converting input terminal and an output terminal. A first resistor network including at least one stage is coupled between the converting input terminal and the output terminal. Each stage of the first resistor network includes a first node, a first current path and a second current path connected to the first node. The first current path of each stage of the first resistor network is connected to the first node of the next stage, the second current path of each stage of the first resistor network is grounded, and the first current path of the first stage of the first resistor network is connected to the converting input terminal. A loading unit is coupled between the converting input terminal and the output terminal.

Abstract: A filter circuit of the present invention provides a transconductance device for outputting a current signal according to an input voltage and a feedback voltage; a transresistance device coupled to the transconductance device for outputting a output voltage according to the current signal; and a feedback device coupled between the transconductance device and the transresistance device for outputting the feedback voltage according to the output voltage. The transresistance device is coupled to the transconductance device via a resistor network comprising a plurality of stages connected serially, wherein each stage of the resistor network comprises: an input node; an output node; a first resistor coupled between the input node and the ground; and a second resistor coupled between the input node and the output node.

Abstract: An image processing device includes a peripheral circuit and an AFE device. The peripheral circuit is coupled to a display card, and the display signals may be inputted to the AFE device, which processes the display signals, via the peripheral circuit. The image signals outputted from the display card are single-ended analog signals including a red signal, a green signal and a blue signal. The AFE device receives the signals and then utilizes its red, green and blue converters to convert the signals into digital ones. It is to be noted that the red, green, and blue converters share the same ground, which is electrically connected to another ground of the peripheral circuit. Thus, the peripheral circuit and the AFE device have the same reference ground level so as to avoid the distortion caused when the image signals are converted from single-ended ones into the differential ones.

Abstract: An image signal processing method adapted to an AFE device, which respectively generates first and second colors of digital signals according to first and second colors of analog signals. First, the first color of odd and even signals and the second color of odd and even signals are generated according to the first and second colors of analog signals, respectively. In a single channel mode, the first color of odd or even signal serves as the first color of digital signal for output, and the second color of odd or even signal serves as the second color of digital signal for output. In a dual channel mode, the first color of odd signal and second color of even signal are synchronously outputted, and the first color of even signal and second color of odd signal are also synchronously outputted. The first color of odd and even signals are combined to form the first color of digital signal, and the second color of odd and even signals are combined to form the second color of digital signal.

Abstract: The line driver with active termination includes: a differential amplifier having an inverting output terminal, a non-inverting output terminal, an inverting input terminal, and a non-inverting input terminal; a first resistor unit coupled to the inverting input terminal; a impedance matching resistor unit coupled to the non-inverting output terminal; and a resistive feedback network, having a plurality of resistors in symmetric configuration. The resistive feedback network further includes: a second resistor unit coupled to the impedance matching resistor unit and the inverting input terminal; a third resistor unit coupled to the non-inverting output terminal and the inverting input terminal; a fourth resistor unit coupled to the impedance matching resistor unit and the inverting input terminal; and a fifth resistor unit coupled to the inverting output terminal and the inverting input terminal.