Patents by Inventor Ju Il Eom
Ju Il Eom has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240021596Abstract: A semiconductor package includes a substrate; a sub semiconductor package disposed over the substrate, the sub semiconductor package including a sub semiconductor chip with chip pads on its active surface that faces the substrate, a sub molding layer that surrounds side surfaces of the sub semiconductor chip, the sub molding layer with a surface that faces the substrate, and redistribution conductive layers that connect to the chip pads and extend under the surface of the sub molding layer, wherein the redistribution conductive layers include a signal redistribution conductive layer that extends toward an edge of the sub molding layer, the signal redistribution conductive layer with a signal redistribution pad on its end portion, and a power redistribution conductive layer that has a length that is shorter than a length of the signal redistribution conductive layer, the power redistribution conductive layer with a power redistribution pad on its end portion; a signal sub interconnector with an upper surface tType: ApplicationFiled: July 12, 2023Publication date: January 18, 2024Applicant: SK hynix Inc.Inventors: Ju Il EOM, Seung Yeop LEE
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Patent number: 11742340Abstract: A semiconductor package includes a substrate; a sub semiconductor package disposed over the substrate, the sub semiconductor package including a sub semiconductor chip with chip pads on its active surface that faces the substrate, a sub molding layer that surrounds side surfaces of the sub semiconductor chip, the sub molding layer with a surface that faces the substrate, and redistribution conductive layers that connect to the chip pads and extend under the surface of the sub molding layer, wherein the redistribution conductive layers include a signal redistribution conductive layer that extends toward an edge of the sub molding layer, the signal redistribution conductive layer with a signal redistribution pad on its end portion, and a power redistribution conductive layer that has a length that is shorter than a length of the signal redistribution conductive layer, the power redistribution conductive layer with a power redistribution pad on its end portion; a signal sub interconnector with an upper surface tType: GrantFiled: January 20, 2021Date of Patent: August 29, 2023Assignee: SK hynix Inc.Inventors: Ju Il Eom, Seung Yeop Lee
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Publication number: 20230197687Abstract: A semiconductor package includes a substrate including a first bonding pad and a first conductive pattern positioned at the same level and in contact with the first bonding pad; a lower semiconductor chip and an upper semiconductor chip stacked over the substrate, the lower and upper semiconductor chips respectively including a first lower chip pad and a first upper chip pad; a first lower bonding wire with first and second ends respectively connected to the first bonding pad and the first lower chip pad; and a first upper bonding wire with a first end connected to the first bonding pad and a second end connected to the first upper chip pad, the first end of the first upper bonding wire is located farther from the lower and upper semiconductor chips and closer to the first conductive pattern than the first end of the first lower bonding wire.Type: ApplicationFiled: February 10, 2023Publication date: June 22, 2023Applicant: SK hynix Inc.Inventors: Byung Jun BANG, Ju Il EOM
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Patent number: 11682643Abstract: A semiconductor chip includes a chip body including a signal input/output circuit unit, a chip pad unit disposed on one surface of the chip body and including first and second chip pads having different surface areas from each other, and a chip pad selection circuit unit disposed in the chip body and electrically connected to the signal input/output circuit unit and the chip pad unit. The chip pad selection circuit unit is configured to select one chip pad of the first and second chip pads and electrically connect the selected one chip pad to the signal input/output circuit unit.Type: GrantFiled: April 26, 2021Date of Patent: June 20, 2023Assignee: SK hynix Inc.Inventors: Ju Il Eom, Woo Jin Lee, Hyung Ho Cho
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Patent number: 11682627Abstract: A semiconductor package includes a package substrate, a lower chip, an interposer, and an upper chip which are stacked on the package substrate, and bonding wires electrically connecting the lower chip to the package substrate. The lower chip includes first and second lower chip pads spaced apart from each other on an upper surface of the lower chip, wire bonding pads bonded to the bonding wires on the upper surface of the lower chip, and lower chip redistribution lines electrically connecting the second lower chip pad to the wire bonding pad. The interposer includes an upper chip connection pad on an upper surface of the interposer, a lower chip connection pad on a lower surface of the interposer, and a through via electrode electrically connecting the upper chip connection pad to the lower chip connection pad.Type: GrantFiled: June 12, 2020Date of Patent: June 20, 2023Assignee: SK hynix Inc.Inventors: Ju Il Eom, Jae Hoon Lee
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Patent number: 11605615Abstract: A semiconductor package includes: a substrate including a first bonding pad and a first conductive pattern positioned at the same level and in contact with the first bonding pad; a lower semiconductor chip and an upper semiconductor chip stacked over the substrate, the lower and upper semiconductor chips respectively including a first lower chip pad and a first upper chip pad; a first lower bonding wire with first and second ends respectively connected to the first bonding pad and the first lower chip pad; and a first upper bonding wire with a first end connected to the first bonding pad and a second end connected to the first upper chip pad, the first end of the first upper bonding wire is located farther from the lower and upper semiconductor chips and closer to the first conductive pattern than the first end of the first lower bonding wire.Type: GrantFiled: August 10, 2021Date of Patent: March 14, 2023Assignee: SK hynix Inc.Inventors: Byung Jun Bang, Ju Il Eom
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Publication number: 20220336420Abstract: A semiconductor package includes: a substrate including a first bonding pad and a first conductive pattern positioned at the same level and in contact with the first bonding pad; a lower semiconductor chip and an upper semiconductor chip stacked over the substrate, the lower and upper semiconductor chips respectively including a first lower chip pad and a first upper chip pad; a first lower bonding wire with first and second ends respectively connected to the first bonding pad and the first lower chip pad; and a first upper bonding wire with a first end connected to the first bonding pad and a second end connected to the first upper chip pad, the first end of the first upper bonding wire is located farther from the lower and upper semiconductor chips and closer to the first conductive pattern than the first end of the first lower bonding wire.Type: ApplicationFiled: August 10, 2021Publication date: October 20, 2022Applicant: SK hynix Inc.Inventors: Byung Jun BANG, Ju Il EOM
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Patent number: 11462511Abstract: A semiconductor package includes a sub semiconductor package disposed over a substrate. The sub semiconductor package includes a sub semiconductor chip with chip pads on its upper surface, a sub molding layer that surrounds the sub semiconductor chip, and a redistribution conductive layer that is connected to each of the chip pads and extends over an upper surface of the sub molding layer. The redistribution conductive layer includes a signal redistribution conductive layer that extends onto an edge of the sub molding layer and has a signal redistribution pad on its end portion and a power redistribution conductive layer with a length that is shorter than a length of the signal redistribution conductive layer. The semiconductor package also includes a sub signal interconnector, sub power interconnector, and at least one main semiconductor chip formed over the sub semiconductor package and electrically connected to the substrate or the sub semiconductor chip.Type: GrantFiled: October 14, 2020Date of Patent: October 4, 2022Assignee: SK hynix Inc.Inventors: Ju Il Eom, Jin Kyoung Park
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Publication number: 20220173735Abstract: A semiconductor chip includes a chip body including a signal input/output circuit, a chip pad structure disposed on a surface of the chip body, the chip pad structure including first and second chip pads, the two chip pads having different surface areas, and a chip pad selection circuit disposed in the chip body and electrically connected to the signal input/output circuit and the chip pad structure. The chip pad selection circuit is configured to selectively and electrically connect one of the first and second chip pads to the signal input/output circuit.Type: ApplicationFiled: October 11, 2021Publication date: June 2, 2022Applicant: SK hynix Inc.Inventors: Ju Il EOM, Woo Jin LEE, Hyung Ho CHO
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Publication number: 20220173061Abstract: A semiconductor chip includes a chip body including a signal input/output circuit unit, a chip pad unit disposed on one surface of the chip body and including first and second chip pads having different surface areas from each other, and a chip pad selection circuit unit disposed in the chip body and electrically connected to the signal input/output circuit unit and the chip pad unit. The chip pad selection circuit unit is configured to select one chip pad of the first and second chip pads and electrically connect the selected one chip pad to the signal input/output circuit unit.Type: ApplicationFiled: April 26, 2021Publication date: June 2, 2022Applicant: SK hynix Inc.Inventors: Ju Il EOM, Woo Jin LEE, Hyung Ho CHO
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Patent number: 11317022Abstract: A photographing method and apparatus is provided. The photographing apparatus includes a photographing unit; a sensing unit for sensing motion of the photographing apparatus; a display unit for displaying at least one guide image for panorama photographing; a controller for controlling the photographing unit to automatically photograph, if a photographing direction that changes in accordance with motion of the photographing apparatus corresponds to one of the at least one guide image; and a storage unit for storing the photographed image data.Type: GrantFiled: April 19, 2021Date of Patent: April 26, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-jun Han, Yong-gook Park, Ju-il Eom, Sang-ok Cha
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Patent number: 11309303Abstract: A semiconductor package includes a substrate and a sub semiconductor package disposed over the substrate. The sub semiconductor package includes a sub semiconductor chip which has chip pads on its active surface facing the substrate, a sub molding layer which surrounds side surfaces of the sub semiconductor chip and has one surface facing the substrate, and redistribution conductive layers which are connected to the chip pads and extend over the one surface of the sub molding layer. The redistribution conductive layers include a signal redistribution conductive layer, which extends onto an edge of the sub molding layer and has a signal redistribution pad on its end portion, and a power redistribution conductive layer, which has a length shorter than a length of the signal redistribution conductive layer and has a power redistribution pad on its end portion.Type: GrantFiled: January 22, 2021Date of Patent: April 19, 2022Assignee: SK hynix Inc.Inventors: Ju Il Eom, Han Jun Bae, Seung Yeop Lee
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Patent number: 11270958Abstract: A semiconductor package includes: a sub semiconductor package disposed over a substrate, the sub semiconductor package including a sub semiconductor chip which has chip pads on its upper surface, a molding layer which surrounds side surfaces of the sub semiconductor chip, and a redistribution layer formed over the sub semiconductor chip and the molding layer, the redistribution layer including redistribution conductive layers which are connected to the chip pads of the sub semiconductor chip and extend onto edges of the molding layer while having redistribution pads on their end portions; first sub package interconnectors connected to the redistribution pads to electrically connect the sub semiconductor chip and the substrate; a capacitor formed in the molding layer and including a first electrode, a second electrode, and a body portion, the first and second electrodes having upper surfaces which are connected to the redistribution conductive layers, respectively.Type: GrantFiled: August 12, 2020Date of Patent: March 8, 2022Assignee: SK hynix Inc.Inventors: Ju Il Eom, Jin Kyoung Park, Han Jun Bae
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Publication number: 20220037304Abstract: A semiconductor package includes a substrate and a sub semiconductor package disposed over the substrate. The sub semiconductor package includes a sub semiconductor chip which has chip pads on its active surface facing the substrate, a sub molding layer which surrounds side surfaces of the sub semiconductor chip and has one surface facing the substrate, and redistribution conductive layers which are connected to the chip pads and extend over the one surface of the sub molding layer. The redistribution conductive layers include a signal redistribution conductive layer, which extends onto an edge of the sub molding layer and has a signal redistribution pad on its end portion, and a power redistribution conductive layer, which has a length shorter than a length of the signal redistribution conductive layer and has a power redistribution pad on its end portion.Type: ApplicationFiled: January 22, 2021Publication date: February 3, 2022Applicant: SK hynix Inc.Inventors: Ju Il EOM, Han Jun BAE, Seung Yeop LEE
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Publication number: 20220028847Abstract: A semiconductor package includes a substrate; a sub semiconductor package disposed over the substrate, the sub semiconductor package including a sub semiconductor chip with chip pads on its active surface that faces the substrate, a sub molding layer that surrounds side surfaces of the sub semiconductor chip, the sub molding layer with a surface that faces the substrate, and redistribution conductive layers that connect to the chip pads and extend under the surface of the sub molding layer, wherein the redistribution conductive layers include a signal redistribution conductive layer that extends toward an edge of the sub molding layer, the signal redistribution conductive layer with a signal redistribution pad on its end portion, and a power redistribution conductive layer that has a length that is shorter than a length of the signal redistribution conductive layer, the power redistribution conductive layer with a power redistribution pad on its end portion; a signal sub interconnector with an upper surface tType: ApplicationFiled: January 20, 2021Publication date: January 27, 2022Applicant: SK hynix Inc.Inventors: Ju Il EOM, Seung Yeop LEE
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Publication number: 20220013499Abstract: A semiconductor package includes a sub semiconductor package disposed over a substrate. The sub semiconductor package includes a sub semiconductor chip with chip pads on its upper surface, a sub molding layer that surrounds the sub semiconductor chip, and a redistribution conductive layer that is connected to each of the chip pads and extends over an upper surface of the sub molding layer. The redistribution conductive layer includes a signal redistribution conductive layer that extends onto an edge of the sub molding layer and has a signal redistribution pad on its end portion and a power redistribution conductive layer with a length that is shorter than a length of the signal redistribution conductive layer. The semiconductor package also includes a sub signal interconnector, sub power interconnector, and at least one main semiconductor chip formed over the sub semiconductor package and electrically connected to the substrate or the sub semiconductor chip.Type: ApplicationFiled: October 14, 2020Publication date: January 13, 2022Applicant: SK hynix Inc.Inventors: Ju Il EOM, Jin Kyoung PARK
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Publication number: 20210366847Abstract: A semiconductor package includes: a sub semiconductor package disposed over a substrate, the sub semiconductor package including a sub semiconductor chip which has chip pads on its upper surface, a molding layer which surrounds side surfaces of the sub semiconductor chip, and a redistribution layer formed over the sub semiconductor chip and the molding layer, the redistribution layer including redistribution conductive layers which are connected to the chip pads of the sub semiconductor chip and extend onto edges of the molding layer while having redistribution pads on their end portions; first sub package interconnectors connected to the redistribution pads to electrically connect the sub semiconductor chip and the substrate; a capacitor formed in the molding layer and including a first electrode, a second electrode, and a body portion, the first and second electrodes having upper surfaces which are connected to the redistribution conductive layers, respectively.Type: ApplicationFiled: August 12, 2020Publication date: November 25, 2021Applicant: SK hynix Inc.Inventors: Ju Il EOM, Jin Kyoung PARK, Han Jun BAE
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Patent number: 11089477Abstract: Methods and apparatus are provided for obtaining a service is provided. Information about an external device is received at a terminal from the external device. It is determined whether the external device has been registered based on the information about the external device. Service information associated with the external device is provided when at least the external device has been registered.Type: GrantFiled: December 18, 2018Date of Patent: August 10, 2021Inventors: Sang-ok Cha, Yong-gook Park, Ho-jun Lee, Tae-young Kang, Hee-chul Jeon, Ju-il Eom, Joo-yoon Bae, Won-young Choi, Sang-gon Song, Kuk-hyun Han, Bum-joo Lee, Seung-hwan Hong
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Publication number: 20210243370Abstract: A photographing method and apparatus is provided.Type: ApplicationFiled: April 19, 2021Publication date: August 5, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-jun HAN, Yong-gook PARK, Ju-il EOM, Sang-ok CHA
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Publication number: 20210167017Abstract: A semiconductor package includes a package substrate, a lower chip, an interposer, and an upper chip which are stacked on the package substrate, and bonding wires electrically connecting the lower chip to the package substrate. The lower chip includes first and second lower chip pads spaced apart from each other on an upper surface of the lower chip, wire bonding pads bonded to the bonding wires on the upper surface of the lower chip, and lower chip redistribution lines electrically connecting the second lower chip pad to the wire bonding pad. The interposer includes an upper chip connection pad on an upper surface of the interposer, a lower chip connection pad on a lower surface of the interposer, and a through via electrode electrically connecting the upper chip connection pad to the lower chip connection pad.Type: ApplicationFiled: June 12, 2020Publication date: June 3, 2021Applicant: SK hynix Inc.Inventors: Ju Il EOM, Jae Hoon LEE