Abstract: A pixel circuit in a display panel includes a drive transistor and a first transistor, a first terminal of the drive transistor is electrically connected to a power signal line, a first terminal of the first transistor is electrically connected to an initialization signal line; a second terminal of the first transistor is electrically connected to the drive transistor, or the second terminal of the first transistor is electrically connected to the light-emitting element; and drive modes of the display panel include a first drive mode, a second drive mode, and a third drive mode, the first drive mode corresponds to a first drive frequency F1 and a first initialization signal Vref1, the second drive mode corresponds to a second drive frequency F2 and a second initialization signal Vref2, and the third drive mode corresponds to a third drive frequency F3 and a third initialization signal Vref3.

Abstract: A pixel circuit in a display panel includes a drive transistor and a first transistor, a first terminal of the drive transistor is electrically connected to a power signal line, a first terminal of the first transistor is electrically connected to an initialization signal line; a second terminal of the first transistor is electrically connected to the drive transistor or a light-emitting element; drive modes of the display panel include an i-th drive mode and a j-th drive mode, and the i-th drive mode corresponds to an i-th drive frequency Fi and an i-th initialization signal Vrefi, the j-th drive mode corresponds to a j-th drive frequency Fj, a signal writing stage in the j-th drive mode corresponds to a j1-th initialization signal Vrefj1, and a light emission holding stage in the j-th drive mode corresponds to a j2-th initialization signal Vrefj2.

Abstract: A pixel circuit in a display panel includes a drive transistor, a first terminal of the drive transistor is electrically connected to a power signal line; and drive modes of the display panel comprise at least a first drive mode, a second drive mode, and a third drive mode, wherein the first drive mode corresponds to a first drive frequency F1 and a first power signal Vdd1, the second drive mode corresponds to a second drive frequency F2 and a second power signal Vdd2, and the third drive mode corresponds to a third drive frequency F3 and a third power signal Vdd3, wherein F 1 > F 2 > F 3 , F 2 - F 3 F 1 - F 3 ? ? "\[LeftBracketingBar]" V dd ? 2 - V dd ? 3 ? "\[RightBracketingBar]" ? "\[LeftBracketingBar]" V dd ? 1 - V dd ? 3 ? "\[RightBracketingBar]" .

Abstract: Provided are a display panel and a display device. The display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a drive module and a first initialization module. The drive module is configured to generate a drive current. The first initialization module is configured to supply a first initialization voltage to a first node. The first node is connected to the light-emitting element. A first control terminal of the first initialization module is configured to transmit the first initialization voltage to the first node in response to a first scan control signal. A display period of the display panel includes a first display stage and a second display stage. In the first display stage, a total effective-pulse duration of the first scan control signal is T1. In the second display stage, the total effective-pulse duration of the first scan control signal is T2. T1<T2.

Abstract: A display panel, a display device, and an optical compensation method are provided. The display panel includes a display area, a light-emitting element, a pixel circuit, and an optical detection unit. The display area includes a first display area and a second display surrounding the first display area. The light-emitting element includes a first light-emitting element in the first display area and a second light-emitting element in the second display area. The pixel circuit includes a first pixel circuit and a second pixel circuit connected to the first and second light-emitting elements, respectively. The number of the first light-emitting elements connected to the first pixel circuit is greater than that of the second light-emitting elements connected to the second pixel circuit. The optical detection unit includes a first optical detection unit for detecting the brightness of the first light-emitting element.

Abstract: A display panel and a display device are provided. The display panel includes pixel circuits. Each pixel circuit includes a driving transistor, a data writing circuit, a light-emitting control circuit, a threshold compensation circuit and a bias adjustment circuit. The driving transistor includes a gate electrically connected to a first node, a first terminal electrically connected to a second node, and a second terminal electrically connected to the third node, and is configured to generate a driving current. The third node is connected to a light-emitting element through the light-emitting control circuit. The bias adjustment circuit is configured to provide a signal of a bias adjustment signal terminal to the second node under control of a signal of a first scanning signal terminal in such a manner that a bias state of the driving transistor is adjusted.

Abstract: Provided are a display panel and a display device. The display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a drive module and a first initialization module. The drive module is configured to generate a drive current. The first initialization module is configured to supply a first initialization voltage to a first node. The first node is connected to the light-emitting element. A first control terminal of the first initialization module is configured to transmit the first initialization voltage to the first node in response to a first scan control signal. A display period of the display panel includes a first display stage and a second display stage. In the first display stage, a total effective-pulse duration of the first scan control signal is T1. In the second display stage, the total effective-pulse duration of the first scan control signal is T2. T1<T2.

Abstract: A display panel includes: first and second display areas; first and second pixel circuits connected to light-emitting elements in the first and second display areas, respectively; and first pixel units and second pixel units, each first pixel unit comprising a first pixel circuit and a light-emitting element connected to the first pixel circuit, and each second pixel unit comprising a second pixel circuit and a light-emitting element connected to the second pixel circuit, wherein each first pixel unit includes the light-emitting element emitting light of a first color, each second pixel unit includes the light-emitting element emitting light of a second color, the first color is different from the second color, each first pixel unit is configured to receive a first power supply signal and a second power supply signal, and each second pixel unit is configured to receive a third power supply signal and a fourth power supply signal.

Abstract: Provided are a tiled display panel and a display device. The tiled display panel includes a transparent substrate and at least two display subpanels. The at least two display subpanels are disposed in at least two tiled regions of the transparent substrate respectively. A first alignment pattern on the transparent substrate includes at least two first sub-patterns. The at least two first sub-patterns are disposed in the at least two tiled regions respectively. A first sub-pattern includes a hollowed-out region. A second alignment pattern on a display subpanel includes at least two second sub-patterns. The shape of a second sub-pattern is the same as the shape of the hollowed-out region. The vertical projection of the second sub-pattern on the transparent substrate is located in the hollowed-out region.

Abstract: Provided are a display panel and a display device. The display panel includes a display area, the display area includes transparent display regions, where film layers in at least two display regions of transparent display regions have different thicknesses, and/or the film layers in the at least two adjacent transparent regions are made of different materials.

Abstract: The application provides a display panel, integrated chip component and display device. The display panel includes: a first display area and a second display area; pixel circuits comprising first pixel circuits and second pixel circuits, the first pixel circuits and the second pixel circuits being configured to provide driving currents for light-emitting elements in the first display area and the second display area, respectively; and first pixel units and second pixel units, each first pixel unit comprising a first pixel circuit and a light-emitting element connected to the first pixel circuit, and each second pixel unit comprising a second pixel circuit and a light-emitting element connected to the second pixel circuit; wherein each first pixel unit is configured to receive a first power supply signal V1 and a second power supply signal V2, V1>V2.

Abstract: Provided are a display panel and a display apparatus. In an embodiment, the display panel includes a substrate and a display medium layer over the substrate. In an embodiment, the display medium layer includes: a microstructure; a plurality of charged particles located in the microstructure; a first electrode at least partially located in the microstructure; and a second electrode at least partially located in the microstructure. In an embodiment, the microstructure has a sidewall not parallel to the substrate and a bottom surface. In an embodiment, the first electrode includes a first side portion located on the sidewall and a first extension portion. In an embodiment, the first extension portion is connected to the first side portion and located on part of the bottom surface.

Abstract: A display panel and a display device are provided. The display panel includes a first substrate, a second substrate arranged opposite to the first substrate, an electrophoresis layer, a liquid-blocking portion and a supporting structure. The electrophoresis layer is arranged between the first substrate and the second substrate and includes multiple electrophoresis particles. The liquid-blocking portion is arranged at an edge of the first substrate and/or the second substrate. The supporting structure is arranged between the first substrate and the second substrate and includes a first supporting portion and a second supporting portion. A height of the first supporting portion is greater than that of the second supporting portion in a direction perpendicular to a plane where the first substrate is located. A minimum distance between the second supporting portion and the liquid-blocking portion is less than that between the first supporting portion and the liquid-blocking portion.

Abstract: A display panel includes at least one pixel circuit and a light emitting element. One pixel circuit includes a driving transistor, and second and third transistors. The second transistor is connected between data line and a source of the driving transistor. The third transistor is connected between voltage adjusting signal line and the source. During a data writing phase, the second transistor is turned on, the data line provides data signal equal to VData to the source, a gate of the driving transistor receives the data signal, and voltage of the gate is VData+Vth. Vth denotes threshold voltage of the driving transistor. During a reset and adjustment phase, the third transistor is turned on, the voltage adjusting signal line provides adjusting voltage to the source, voltage of the source of the driving transistor is VJ, and the voltage of the gate remains VData+Vth. VData+Vth?VJ??2V.

Abstract: A pixel circuit in a display panel includes a drive transistor, a first terminal of the drive transistor is electrically connected to a power signal line; and drive modes of the display panel comprise at least a first drive mode, a second drive mode, and a third drive mode, wherein the first drive mode corresponds to a first drive frequency F1 and a first power signal Vdd1, the second drive mode corresponds to a second drive frequency F2 and a second power signal Vdd2, and the third drive mode corresponds to a third drive frequency F3 and a third power signal Vdd3, wherein F 1 > F 2 > F 3 , F 2 - F 3 F 1 - F 3 ? ? "\[LeftBracketingBar]" V dd ? 2 - V dd ? 3 ? "\[RightBracketingBar]" ? "\[LeftBracketingBar]" V dd ? 1 - V dd ? 3 ? "\[RightBracketingBar]" .

Abstract: A pixel circuit in a display panel includes a drive transistor and a first transistor, a first terminal of the drive transistor is electrically connected to a power signal line, a first terminal of the first transistor is electrically connected to an initialization signal line; a second terminal of the first transistor is electrically connected to the drive transistor or a light-emitting element; drive modes of the display panel include an i-th drive mode and a j-th drive mode, and the i-th drive mode corresponds to an i-th drive frequency Fi and an i-th initialization signal Vrefi, the j-th drive mode corresponds to a j-th drive frequency Fj, a signal writing stage in the j-th drive mode corresponds to a j1-th initialization signal Vrefj1, and a light emission holding stage in the j-th drive mode corresponds to a j2-th initialization signal Vrefj2.

Abstract: A pixel circuit in a display panel includes a drive transistor and a first transistor, a first terminal of the drive transistor is electrically connected to a power signal line, a first terminal of the first transistor is electrically connected to an initialization signal line; a second terminal of the first transistor is electrically connected to the drive transistor, or the second terminal of the first transistor is electrically connected to the light-emitting element; and drive modes of the display panel include a first drive mode, a second drive mode, and a third drive mode, the first drive mode corresponds to a first drive frequency F1 and a first initialization signal Vref1, the second drive mode corresponds to a second drive frequency F2 and a second initialization signal Vref2, and the third drive mode corresponds to a third drive frequency F3 and a third initialization signal Vref3.

Abstract: A display panel and a display device are provided. One pixel circuit of the display panel includes a driving transistor, a second transistor, a third transistor, a reset module, and a first light-emission controlling module. The second transistor is connected between a data line and a source of the driving transistor, the third transistor is connected between a voltage adjusting signal line and the source of the driving transistor, the reset module is connected between a reset voltage input terminal and a gate of the driving transistor, and the first light-emission controlling module is connected between a first power supply terminal and the source of the driving transistor. An operation process of the display panel includes a light emitting phase, a data writing phase, a reset and adjustment phase, and a reset phase.

Abstract: A display panel and a display apparatus are provided in the present disclosure. The display panel includes a first display region and a light-blocking layer. The first display region includes a plurality of light-transmitting regions and a plurality of pixel regions; and a transmittance of a light-transmitting region is greater than a transmittance of a pixel region. The light-blocking layer includes a first opening region and a second opening region; along a direction perpendicular to a plane of the display panel, the first opening region is overlapped with the light-transmitting region, and the second opening region is overlapped with the pixel region; and along a direction in parallel with the plane of the display panel, a minimum distance between the light-transmitting region and the pixel region is D1, and a minimum distance between two adjacent pixel regions is D2, where D1<D2.

Abstract: Provided are a display panel and a display device. The display panel includes a light-emitting element and a pixel drive circuit electrically connected to the light-emitting element. The pixel drive circuit includes a drive transistor and a first reset module. The drive transistor is configured to control a drive current. The first reset module is connected to a first node and configured to provide a first reset voltage to the first node. The light-emitting element is connected to the first node. A working mode of the display panel comprise a first drive mode. A display frame in the first drive mode includes a valid frame and an invalid frame. In the first drive mode, a first reset voltage for the valid frame is different from a first reset voltage for the invalid frame.