Abstract: A system and method for measuring three-dimensional (3D) coordinate values of an environment is provided. The system includes a movable base unit a first scanner and a second scanner. One or more processors performing a method that includes causing the first scanner to determine first plurality of coordinate values in a first frame of reference based at least in part on a measurement by at least one sensor. The second scanner determines a second plurality of 3D coordinate values in a second frame of reference as the base unit is moved from a first position to a second position. The determining of the first coordinate values and the second plurality of 3D coordinate values being performed simultaneously. The second plurality of 3D coordinate values are registered in a common frame of reference based on the first plurality of coordinate values.

Abstract: A system and method for measuring three-dimensional (3D) coordinate values of an environment is provided. The system includes a movable base unit a first scanner and a second scanner. One or more processors performing a method that includes causing the first scanner to determine first plurality of coordinate values in a first frame of reference based at least in part on a measurement by at least one sensor. The second scanner determines a second plurality of 3D coordinate values in a second frame of reference as the base unit is moved from a first position to a second position. The determining of the first coordinate values and the second plurality of 3D coordinate values being performed simultaneously. The second plurality of 3D coordinate values are registered in a common frame of reference based on the first plurality of coordinate values.

Abstract: A system and method for measuring three-dimensional (3D) coordinate values of an environment is provided. The system includes a movable base unit a first scanner and a second scanner. One or more processors performing a method that includes causing the first scanner to determine first plurality of coordinate values in a first frame of reference based on an emitted first beam of light and a received first reflected light. The second scanner determines a second plurality of 3D coordinate values in a second frame of reference as the base unit is moved from a first position to a second position. The determining of the first coordinate values and the second plurality of 3D coordinate values being performed simultaneously. The second plurality of 3D coordinate values are registered in a common frame of reference based on the first plurality of coordinate values.

Abstract: A converter operable to convert an input voltage at an input node to an output voltage at an output node coupled to a load by switching on and off a transistor at a switching frequency, the converter comprising: an error amplifier circuit having a first input coupled to a reference voltage, a second input coupled to the output node through a resistive divider, a first output operable to output a control current and a second output operable to output a current equivalent to the control current; a peak current comparator circuit having a first input coupled to the second output of the error amplifier circuit, a second input and an output, the second input is coupled to the input node through an inductor; an off-time timer circuit having an input coupled to the first output of the error amplifier circuit and an output, the off-time timer circuit operable to set the switching frequency based on the control current; and a control circuit having a first input coupled to the output of the peak current comparator cir

Abstract: According to one embodiment, a three-dimensional (3D) measuring device is provided. The 3D measuring device includes a processor system that is configured to generate a point cloud representing multiple surfaces. The point cloud includes multiple scan points. Generating the point cloud includes receiving spherical coordinates for a scan point, the spherical coordinates comprising a distance (r), a polar angle (?), and an azimuth angle (?). Generating the point cloud further includes homogenizing a scan point density of the surfaces by filtering the scan points. The homogenizing includes computing a value (p) for the scan point based on the spherical coordinates. Based on the value exceeding a predetermined threshold, storing the scan point as part of the point cloud, and based on the value not exceeding the predetermined threshold, discarding the scan point.

Abstract: A switching converter having a voltage input, a voltage output and a transistor connected between the voltage input and the voltage output, the switching converter including a control circuit comprising: a gate driver having an input, a first voltage supply input, a second voltage supply input and an output operable to be connected to a control terminal of the transistor; a bootstrap capacitor connected between the first voltage supply input and the second voltage supply input; and a charge pump having an input operable to be connected to the voltage input and an output connected to the first voltage supply input.

Abstract: A gate driver for a high-side NMOS power transistor in a DC/DC boost converter includes first and second switches coupled in series between an output pin and the gate of the high-side transistor. A third switch is coupled between the gate and a switch-node between the high-side and low-side transistors, the switch node also being coupled to an input pin. Fourth and fifth switches are coupled in series between the output pin and a clamp pin. Sixth and seventh switch are coupled in series between the output pin and a ground pin. First and second bootstrap capacitors have respective first terminals coupled to a first node between the first and second switches. The first capacitor has a second terminal coupled to a node between the fourth and fifth switches; the second capacitor has a second terminal coupled to a node between the sixth and seventh switches.

Abstract: A system and method for measuring three-dimensional (3D) coordinate values of an environment is provided. The system includes a movable base unit a first scanner and a second scanner. One or more processors performing a method that includes causing the first scanner to determine first plurality of coordinate values in a first frame of reference based on an emitted first beam of light and a received first reflected light. The second scanner determines a second plurality of 3D coordinate values in a second frame of reference as the base unit is moved from a first position to a second position. The determining of the first coordinate values and the second plurality of 3D coordinate values being performed simultaneously. The second plurality of 3D coordinate values are registered in a common frame of reference based on the first plurality of coordinate values.

Abstract: A system and method for measuring three-dimensional (3D) coordinate values of an environment is provided. The system includes a movable base unit and a 2D scanner. A 3D scanner is coupled to the base unit, the 3D scanner measuring 3D coordinates and grey values of surfaces in the environment, the 3D scanner operating in either a compound or helical mode. Processors perform a method comprising: causing the 3D scanner to measure a first 3D coordinate values while operating in one of the compound or helical mode as the base unit is moved from the first to the second position; causing the 3D scanner to measure a second 3D coordinate values while operating in compound mode when the base unit is stationary between the first and second position; and registering the first 3D coordinate values and second 3D coordinate values into a single frame of reference.

Abstract: A converter operable to convert an input voltage at an input node to an output voltage at an output node coupled to a load by switching on and off a transistor at a switching frequency, the converter comprising: an error amplifier circuit having a first input coupled to a reference voltage, a second input coupled to the output node through a resistive divider, a first output operable to output a control current and a second output operable to output a current equivalent to the control current; a peak current comparator circuit having a first input coupled to the second output of the error amplifier circuit, a second input and an output, the second input is coupled to the input node through an inductor; an off-time timer circuit having an input coupled to the first output of the error amplifier circuit and an output, the off-time timer circuit operable to set the switching frequency based on the control current; and a control circuit having a first input coupled to the output of the peak current comparator cir

Abstract: According to one embodiment, a three-dimensional (3D) measuring device is provided. The 3D measuring device includes a processor system that is configured to generate a point cloud representing multiple surfaces. The point cloud includes multiple scan points. Generating the point cloud includes receiving spherical coordinates for a scan point, the spherical coordinates comprising a distance (r), a polar angle (?), and an azimuth angle (?). Generating the point cloud further includes homogenizing a scan point density of the surfaces by filtering the scan points. The homogenizing includes computing a value (p) for the scan point based on the spherical coordinates. Based on the value exceeding a predetermined threshold, storing the scan point as part of the point cloud, and based on the value not exceeding the predetermined threshold, discarding the scan point.

Abstract: A power supply system can include at least one power switch to generate an output current based on an input voltage in response to a switching signal to generate an output voltage. A feedback system generates a feedback current based on the output voltage. A mode detector generates a control current associated with the output current based on the feedback current and selects between a pulse-width modulation (PWM) mode and a pulse mode based on an amplitude of the control current. The PWM mode is associated with a sequential on-time and off-time of the at least one power switch, and the pulse mode is associated with adding an idle time between the on-time and the off-time of the at least one power switch based on the switching signal. A gate driver system generates the switching signal based on the mode.

Abstract: A gate driver for a high-side NMOS power transistor in a DC/DC boost converter includes first and second switches coupled in series between an output pin and the gate of the high-side transistor. A third switch is coupled between the gate and a switch-node between the high-side and low-side transistors, the switch node also being coupled to an input pin. Fourth and fifth switches are coupled in series between the output pin and a clamp pin. Sixth and seventh switch are coupled in series between the output pin and a ground pin. First and second bootstrap capacitors have respective first terminals coupled to a first node between the first and second switches. The first capacitor has a second terminal coupled to a node between the fourth and fifth switches; the second capacitor has a second terminal coupled to a node between the sixth and seventh switches.

Abstract: A gate driver for a high-side NMOS power transistor in a DC/DC boost converter includes first and second switches coupled in series between an output pin and the gate of the high-side transistor. A third switch is coupled between the gate and a switch-node between the high-side and low-side transistors, the switch node also being coupled to an input pin. Fourth and fifth switches are coupled in series between the output pin and a clamp pin. Sixth and seventh switch are coupled in series between the output pin and a ground pin. First and second bootstrap capacitors have respective first terminals coupled to a first node between the first and second switches. The first capacitor has a second terminal coupled to a node between the fourth and fifth switches; the second capacitor has a second terminal coupled to a node between the sixth and seventh switches.

Abstract: A gate driver for a high-side NMOS power transistor in a DC/DC boost converter includes first and second switches coupled in series between an output pin and the gate of the high-side transistor. A third switch is coupled between the gate and a switch-node between the high-side and low-side transistors, the switch node also being coupled to an input pin. Fourth and fifth switches are coupled in series between the output pin and a clamp pin. Sixth and seventh switch are coupled in series between the output pin and a ground pin. First and second bootstrap capacitors have respective first terminals coupled to a first node between the first and second switches. The first capacitor has a second terminal coupled to a node between the fourth and fifth switches; the second capacitor has a second terminal coupled to a node between the sixth and seventh switches.

Abstract: A switch-node rising edge detection circuit is provided for a switched-mode DC/DC boost converter. A high-side gate-driver couples a gate of the high-side NMOS power transistor to either a first terminal of a bootstrap capacitor or the switch-node. The detection circuit includes an AND gate that receives an activation signal on a first input and provides a switching signal to the high-side gate-driver. A PMOS transistor is coupled in series with an inverter between the first terminal of the bootstrap capacitor and a second input of the AND gate. The inverter receives supply voltages from the first terminal of the bootstrap capacitor and the switch-node. The gate of the PMOS transistor receives the activation signal. An NMOS transistor is coupled between an output voltage and a node between the PMOS transistor and the inverter. A gate of the NMOS transistor is coupled to the bootstrap capacitor's first terminal.

Abstract: A system and method for measuring three-dimensional (3D) coordinate values of an environment is provided. The system includes a movable base unit and a 2D scanner. A 3D scanner is coupled to the base unit, the 3D scanner measuring 3D coordinates and grey values of surfaces in the environment, the 3D scanner operating in either a compound or helical mode. Processors perform a method comprising: causing the 3D scanner to measure a first 3D coordinate values while operating in one of the compound or helical mode as the base unit is moved from the first to the second position; causing the 3D scanner to measure a second 3D coordinate values while operating in compound mode when the base unit is stationary between the first and second position; and registering the first 3D coordinate values and second 3D coordinate values into a single frame of reference.

Abstract: A power supply system can include at least one power switch to generate an output current based on an input voltage in response to a switching signal to generate an output voltage. A feedback system generates a feedback current based on the output voltage. A mode detector generates a control current associated with the output current based on the feedback current and selects between a pulse-width modulation (PWM) mode and a pulse mode based on an amplitude of the control current. The PWM mode is associated with a sequential on-time and off-time of the at least one power switch, and the pulse mode is associated with adding an idle time between the on-time and the off-time of the at least one power switch based on the switching signal. A gate driver system generates the switching signal based on the mode.

Abstract: A level shifter with reduced propagation delay. A level shifter includes a signal input terminal, a first signal output node, a first transistor, a second transistor, a third transistor, and a first capacitor. The first transistor includes a control terminal coupled to the signal input terminal. The second transistor includes an output terminal coupled to an input terminal of the first transistor. The first capacitor includes a bottom plate coupled to an input terminal of the second transistor. The third transistor includes a control terminal coupled to a top plate of the first capacitor, and an output terminal coupled to the first signal output node.

Abstract: A level shifter with reduced propagation delay. A level shifter includes a signal input terminal, a first signal output node, a first transistor, a second transistor, a third transistor, and a first capacitor. The first transistor includes a control terminal coupled to the signal input terminal. The second transistor includes an output terminal coupled to an input terminal of the first transistor. The first capacitor includes a bottom plate coupled to an input terminal of the second transistor. The third transistor includes a control terminal coupled to a top plate of the first capacitor, and an output terminal coupled to the first signal output node.