Abstract: Systems, methods, and apparatuses for resource bandwidth monitoring and control are described. For example, in some embodiments, an apparatus comprising a requestor device to send a credit based request, a receiver device to receive and consume the credit based request, and a delay element in a return path between the requestor and receiver devices, the delay element to delay a credit based response from the receiver to the requestor are detailed.

Abstract: Methods and apparatus relating to dynamic allocation schemes applied to a memory side cache for bandwidth and/or performance optimization are described. In an embodiment, a memory side cache stores a portion of data to be stored in a main memory. Logic circuitry determines whether to allocate a portion of the memory side cache for use by a device. The remaining portion of the memory side cache is to be used by a processor. The allocated portion of the memory side cache is reallocated for use by the processor in response to a determination that the allocated portion of the memory side cache is no longer to be used by the device. Other embodiments are also disclosed and claimed.

Abstract: Techniques and mechanisms for selectively configuring an integrated circuit (IC) chip to provide tag array functionality and/or cache array functionality. In an embodiment, an IC chip comprises a first array of memory cells, a second array of memory cells, and a cache controller. Based on whether the IC chip is coupled to another IC chip, selector circuitry of the IC chip configures one of multiple possible modes of the cache controller. A first mode of the multiple modes is to provide tag array functionality with the first array, and cache array functionality with the second memory cell array. A second mode of the multiple modes is to provide tag array functionality with the second memory cell array, and cache array functionality with a remote array of memory cells. In another embodiment, the cache controller is reconfigured to another mode based on a change to a power consumption characteristic.

Abstract: Embodiments of apparatuses, methods, and systems for performance monitoring in heterogenous systems are described. In an embodiment, an apparatus includes a plurality of performance counters to generate a plurality of unweighted event counts; a weights storage to store a plurality of weight values, each weight value corresponding to an unweighted event count; a plurality of weighting units, each weighting unit to weight a corresponding unweighted event count based on a corresponding weight value to generate one of a plurality of weighted event counts; and a work counter to receive the weighted event counts and generate a measured work amount.

Abstract: Techniques and mechanisms for providing a thread scheduling hint to an operating system of a processor which comprises first cores and second cores. In an embodiment, the first cores are of a first type which corresponds to a first range of sizes, and the second cores are of a second type which corresponds to a second range of sizes smaller than the first range of sizes. A power control unit (PCU) of the processor is to detect that an inefficiency, of a first operational mode of the processor, would exist while an indication of an amount of power, to be available to the processor, is below a threshold. Based on the detecting, the PCU hints to an executing software process that a given core is to be included in, or omitted from, a pool of cores available for thread scheduling. The hint indicates the given core based on a relative prioritization of the first core type and the second core type.

Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors.

Abstract: Methods, apparatus, systems, and articles of manufacture to increase boot performance are disclosed. An example apparatus including instructions stored in the apparatus; and processor circuitry to execute the instructions to: during a boot process: identify a boot task that is to be performed during the boot process; execute the boot task using a first processor component; collect data corresponding to the execution of the boot task on the first processor component; categorize the boot task based on the collected data; and generate an entry for a boot table based on the categorization, the boot table used to schedule the boot task on at least one of the first processor component or a second processor component different than the first processor component based on the categorization.

Abstract: Systems, methods, and apparatuses for resource bandwidth monitoring and control are described. For example, in some embodiments, an apparatus comprising a requestor device to send a credit based request, a receiver device to receive and consume the credit based request, and a delay element in a return path between the requestor and receiver devices, the delay element to delay a credit based response from the receiver to the requestor are detailed.

Abstract: Embodiments of apparatuses, methods, and systems for performance monitoring in heterogenous systems are described. In an embodiment, an apparatus includes a plurality of performance counters to generate a plurality of unweighted event counts; a weights storage to store a plurality of weight values, each weight value corresponding to an unweighted event count; a plurality of weighting units, each weighting unit to weight a corresponding unweighted event count based on a corresponding weight value to generate one of a plurality of weighted event counts; and a work counter to receive the weighted event counts and generate a measured work amount.

Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors.

Abstract: Method and apparatus for per-agent control and quality of service of shared resources in a chip multiprocessor platform is described herein. One embodiment of a system includes: a plurality of core and non-core requestors of shared resources, the shared resources to be provided by one or more resource providers, each of the plurality of core and non-core requestors to be associated with a resource-monitoring tag and a resource-control tag; a mapping table to store the resource monitoring and control tags associated with each non-core requestor; and a tagging circuitry to receive a resource request sent from a non-core requestor to a resource provider, the tagging circuitry to responsively modify the resource request to include the resource-monitoring and resource-control tags associated with the non-core requestor in accordance to the mapping table and send the modified resource request to the resource provider.

Abstract: An apparatus is described. The apparatus includes a memory controller to interface to a multi-level system memory having first and second different cache structures. The memory controller has circuitry to service a read request by concurrently performing a look-up into the first and second different cache structures for a cache line that is targeted by the read request.

Abstract: One embodiment provides an apparatus. The apparatus includes first memory controller circuitry to control read and/or write access to first memory circuitry via a first conductive bus. The apparatus includes second memory controller circuitry to control read and/or write access to second memory circuitry via a second conductive bus. The apparatus includes power control circuitry coupled to the first memory controller circuitry and the second memory controller circuitry. The power control circuitry transfers data from the second memory circuitry with the second memory controller circuitry via the second conductive bus to the first memory circuitry with the first memory controller circuitry via the first conductive bus. The power control circuitry powers down the second memory circuitry after the transfer of the data from the second memory circuitry to the first memory circuitry. The power control circuitry decreases power consumption of the apparatus and may increase batter life of the apparatus.

Abstract: Cache behavior for secure memory repartitioning systems is described. Implementations may include a processing core and a memory controller coupled between the processor core and a memory device. The processor core is to receive a memory access request to a page in the memory device, the memory access request comprising a first guarded attribute (GA) indicator indicating whether the page is a secure page belonging to an enclave, determine whether the first GA indicator matches a second GA indicator in a cache line entry corresponding to the page, the cache line entry comprised in a cache, and responsive to a determination that the first GA indicator does not match the second GA indicator, apply an eviction policy to the cache line entry based on whether the cache line is indicated as a dirty cache line and accessing second data in the memory device for the page.

Abstract: One embodiment provides an apparatus. The apparatus includes first memory controller circuitry to control read and/or write access to first memory circuitry via a first conductive bus. The apparatus includes second memory controller circuitry to control read and/or write access to second memory circuitry via a second conductive bus. The apparatus includes power control circuitry coupled to the first memory controller circuitry and the second memory controller circuitry. The power control circuitry transfers data from the second memory circuitry with the second memory controller circuitry via the second conductive bus to the first memory circuitry with the first memory controller circuitry via the first conductive bus. The power control circuitry powers down the second memory circuitry after the transfer of the data from the second memory circuitry to the first memory circuitry. The power control circuitry decreases power consumption of the apparatus and may increase batter life of the apparatus.

Abstract: Systems and methods are disclosed for initialization of a processor. Embodiments relate to alleviating any BIOS code size limitation. In one example, a system includes a memory having stored thereon a basic input/output system (BIOS) program comprising a readable code region and a readable and writeable data stack, a circuit coupled to the memory and to: read, during a boot mode and while using a cache as RAM (CAR), at least one datum from each cache line of the data stack, and write at least one byte of each cache line of the data stack to set a state of each cache line of the data stack to modified, enter a no-modified-data-eviction mode to protect modified data from eviction, and to allow eviction and replacement of readable data, and begin reading from the readable code region and executing the BIOS program after entering the no-modified-data-eviction mode.

Abstract: Method and apparatus for per-agent control and quality of service of shared resources in a chip multiprocessor platform is described herein. One embodiment of a system includes: a plurality of core and non-core requestors of shared resources, the shared resources to be provided by one or more resource providers, each of the plurality of core and non-core requestors to be associated with a resource-monitoring tag and a resource-control tag; a mapping table to store the resource monitoring and control tags associated with each non-core requestor; and a tagging circuitry to receive a resource request sent from a non-core requestor to a resource provider, the tagging circuitry to responsively modify the resource request to include the resource-monitoring and resource-control tags associated with the non-core requestor in accordance to the mapping table and send the modified resource request to the resource provider.

Abstract: Systems and methods for cache allocation with code and data prioritization. An example system may comprise: a cache; a processing core, operatively coupled to the cache; and a cache control logic, responsive to receiving a cache fill request comprising an identifier of a request type and an identifier of a class of service, to identify a subset of the cache corresponding to a capacity bit mask associated with the request type and the class of service.

Abstract: An apparatus is described. The apparatus includes a memory controller to interface to a multi-level system memory having first and second different cache structures. The memory controller has circuitry to service a read request by concurrently performing a look-up into the first and second different cache structures for a cache line that is targeted by the read request.

Abstract: Systems and methods are disclosed for initialization of a processor. Embodiments relate to alleviating any BIOS code size limitation. In one example, a system includes a memory having stored thereon a basic input/output system (BIOS) program comprising a readable code region and a readable and writeable data stack, a circuit coupled to the memory and to: read, during a boot mode and while using a cache as RAM (CAR), at least one datum from each cache line of the data stack, and write at least one byte of each cache line of the data stack to set a state of each cache line of the data stack to modified, enter a no-modified-data-eviction mode to protect modified data from eviction, and to allow eviction and replacement of readable data, and begin reading from the readable code region and executing the BIOS program after entering the no-modified-data-eviction mode.