Abstract: Systems and methods for cache allocation with code and data prioritization. An example system may comprise: a cache; a processing core, operatively coupled to the cache; and a cache control logic, responsive to receiving a cache fill request comprising an identifier of a request type and an identifier of a class of service, to identify a subset of the cache corresponding to a capacity bit mask associated with the request type and the class of service.

Abstract: Systems, methods, and apparatuses for resource bandwidth monitoring and control are described. For example, in some embodiments, an apparatus comprising a requestor device to send a credit based request, a receiver device to receive and consume the credit based request, and a delay element in a return path between the requestor and receiver devices, the delay element to delay a credit based response from the receiver to the requestor are detailed.

Abstract: An apparatus and method are described for detecting and correcting instruction fetch errors within a processor core. For example, in one embodiment, an instruction processing apparatus for detecting and recovering from instruction fetch errors comprises, the instruction processing apparatus performing the operations of: detecting an error associated with an instruction in response to an instruction fetch operation; and determining if the instruction is from a speculative access, wherein if the instruction is not from a speculative access, then responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core.

Abstract: Methods and apparatus relating to adaptive admission control for on die interconnect are described. In one embodiment, admission control logic determines whether to cause a change in an admission rate of requests from one or more sources of data based at least in part on comparison of a threshold value and resource utilization information. The resource utilization information is received from a plurality of resources that are shared amongst the one or more sources of data. The threshold value is determined based at least in part on a number of the plurality of resources that are determined to be in a congested condition. Other embodiments are also disclosed.

Abstract: Hybrid multi-level memory architecture technologies are described. A System on Chip (SOC) includes multiple functional units and a multi-level memory controller (MLMC) coupled to the functional units. The MLMC is coupled to a hybrid multi-level memory architecture including a first-level dynamic random access memory (DRAM) (near memory) that is located on-package of the SOC and a second-level DRAM (far memory) that is located off-package of the SOC. The MLMC presents the first-level DRAM and the second-level DRAM as a contiguous addressable memory space and provides the first-level DRAM to software as additional memory capacity to a memory capacity of the second-level DRAM. The first-level DRAM does not store a copy of contents of the second-level DRAM.

Abstract: In an embodiment, a processor includes a core to execute instructions, where the core includes a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, a restriction logic to receive a restriction command and to reduce delivery of the first clock signal to at least one of the plurality of units. The restriction logic may cause the first clock signal to be distributed to the plurality of units at a lower frequency than a frequency of the first clock signal. Other embodiments are described and claimed.

Abstract: An apparatus for debugging internal signals of integrated circuits is presented. In one embodiment, the apparatus comprises a number of vector registers associated with states of a state machine. A group of registers, associated with a state of the state machine, comprises a mask register an arm register. A comparator compares debug data with contents of the mask register and the arm register to determine a comparison result to be stored in one or more bit positions of the vector register. The apparatus further comprises a triggering logic unit to determine whether or not to trigger a fire event based on the vector registers.

Abstract: A processor may comprise a core area, a control unit, an uncore area. The core area may comprise multiple processing cores and line-fill buffers. A first processing core of the core area may store a first weakly ordered transaction in a first line-fill buffer. The firs processing core may offload the first weakly ordered transaction to the extended buffer space provisioned in the uncore area after receiving a request from the uncore area. The first processing core may then de-allocate the first line-fill buffer after the first weakly ordered transaction is offloaded to the extended buffer space. The uncore may then post the first weakly ordered transaction to a memory or a memory system. The control unit may track the first weakly ordered transaction to ensure that the first weakly ordered transaction is posted to the memory or the system.

Abstract: An apparatus for debugging internal signals of integrated circuits is presented. In one embodiment, the apparatus comprises a number of vector registers associated with states of a state machine. A group of registers, associated with a state of the state machine, comprises a mask register an arm register. A comparator compares debug data with contents of the mask register and the arm register to determine a comparison result to be stored in one or more bit positions of the vector register. The apparatus further comprises a triggering logic unit to determine whether or not to trigger a fire event based on the vector registers.

Abstract: In one embodiment, the present invention includes a method for receiving an indication of a pending capacity eviction from a caching agent, determining whether an invalidating writeback transaction from the caching agent is likely for a cache line associated with the pending capacity eviction, and if so moving a snoop filter entry associated with the cache line from a snoop filter to a staging area. Other embodiments are described and claimed.

Abstract: Embodiments of the present invention provide a resource management mechanism to monitor the availability of resources, detect the cause of a rejection, distinguish between different types of rejections, and manage the different types accordingly. For example, a queue manager in accordance with embodiments of the invention may be able to classify rejected requests, for example, as either a “long reject” or a “short reject” based on the cause of the rejection and the amount of time the rejection conditions are expected to remain valid. A short reject request may be rescheduled in an appropriate service queue, while a long reject request may be suspended in a reject queue. Other features are described and claimed.

Abstract: A processor may comprise a core area, a control unit, an uncore area. The core area may comprise multiple processing cores and line-fill buffers. A first processing core of the core area may store a first weakly ordered transaction in a first line-fill buffer. The firs processing core may offload the first weakly ordered transaction to the extended buffer space provisioned in the uncore area after receiving a request from the uncore area. The first processing core may then de-allocate the first line-fill buffer after the first weakly ordered transaction is offloaded to the extended buffer space. The uncore may then post the first weakly ordered transaction to a memory or a memory system. The control unit may track the first weakly ordered transaction to ensure that the first weakly ordered transaction is posted to the memory or the system.

Abstract: In one embodiment, the present invention includes a method for receiving an indication of a pending capacity eviction from a caching agent, determining whether an invalidating writeback transaction from the caching agent is likely for a cache line associated with the pending capacity eviction, and if so moving a snoop filter entry associated with the cache line from a snoop filter to a staging area. Other embodiments are described and claimed.

Abstract: Briefly, a method, main processing unit and a computer system to report a failure in a bit of a memory line by updating first and second counters for a first time and a second time correction of bit failures in a line, respectively. The updating of first and second counters after a third time correction of bit failure in the line is disabled.

Abstract: In one embodiment, the present invention includes a method including initiating a cleaning operation to clear a first processor core of a system of pending operations, and preventing injection of new events into a second processor core if the cleaning operation is not serviced in the first processor core. In this way, lock situations may be broken without their detection. Other embodiments are described and claimed.

Abstract: Briefly, a method, main processing unit and a computer system to report a failure in a bit of a memory line by updating first and second counters for a first time and a second time correction of bit failures in a line, respectively. The updating of first and second counters after a third time correction of bit failure in the line is disabled.

Abstract: Embodiments of the present invention provide a resource management mechanism to monitor the availability of resources, detect the cause of a rejection, distinguish between different types of rejections, and manage the different types accordingly. For example, a queue manager in accordance with embodiments of the invention may be able to classify rejected requests, for example, as either a “long reject” or a “short reject” based on the cause of the rejection and the amount of time the rejection conditions are expected to remain valid. A short reject request may be rescheduled in an appropriate service queue, while a long reject request may be suspended in a reject queue. Other features are described and claimed.

Abstract: Some embodiments of the invention provide devices, systems and methods of cache coherence. For example, an apparatus in accordance with an embodiment of the invention includes a memory to store a memory line; and a cache controller logic to assign a first cache coherence state to the memory line in relation to a first component, and to assign a second, different, cache coherence state to the memory line in relation to a second, different, component.

Abstract: In one embodiment, the present invention includes a method including initiating a cleaning operation to clear a first processor core of a system of pending operations, and preventing injection of new events into a second processor core if the cleaning operation is not serviced in the first processor core. In this way, lock situations may be broken without their detection. Other embodiments are described and claimed.

Abstract: Systems and methods of dynamic memory for power reduction are described with respect to a memory with a coupled sleep device. In one embodiment, the operating requirements can reflect amount of memory required to perform commensurate operations. Memory power management logic is used to coordinate memory requirements with operating requirements. The sleep device is able to enable or disable the memory based on the requirements to reduce power consumption.