Abstract: The subject technology is directed to clock calibration systems and methods. In an embodiment, the subject technology provides an apparatus for clock calibration to minimize timing discrepancies between even and odd clock edges. The apparatus includes a first data path configured to generate a first signal, the first signal comprising a first edge and a second edge associated with even and odd clock cycles, respectively. A calibration circuit is coupled to the first data path and configured to determine a timing difference between the first edge and the second edge to calculate even-odd jitter (EOJ). This configuration enables precise calibration to reduce EOJ and ensure accurate synchronization of clock signals in high-speed communication systems.

Abstract: A power supply circuit board is provided with a step-down converter and a power input port, and the step-down converter is electrically connected to the power input port. The power input port is configured to receive an input voltage, and the step-down converter is configured to convert the input voltage into a voltage required by a chip component. The power supply circuit board is further provided with a first connector, and the first connector is electrically connected to the step-down converter. The first connector mates with a second connector of a voltage regulator in the chip component, the first connector is disposed opposite to the second connector, and the chip component obtains, through the first connector, the voltage required by the chip component.

Abstract: An apparatus for canceling clock-to-signal interference in a multi-lane SerDes comprising an analog front-end circuit receiving an input signal from a signal path mixed with interference from a clock path. The apparatus includes a phase interpolator circuit implemented in the clock path to generate multiple phases of a clock signal and to provide a timing rotated by the phases for a track-and-hold circuit to sample the input signal and the interference in every cycle. The apparatus also includes an analog-to-digital converter configured to digitize the input signal and the interference to provide an ADC output and a digital-interference-cancellation circuit configured to demultiplex the ADC output and detect a baseline offset associated with the interference sampled at one of the phases in each demultiplexed path using a digital loop to calibrate the baseline offset.

Abstract: A fog collecting box and a bubble machine are provided. The fog collecting box is mounted in the bubble machine. The fog collecting box includes an inlet, an outlet, and a channel defined in the fog collecting box. The channel is communicated between the inlet and the outlet of the fog collecting box. The channel includes at least one bending section, so that a length of the channel is greater than a linear distance between the inlet and the outlet of the fog collecting box.

Abstract: A reference buffer with wide output voltage and current range is provided. A reference buffer includes an error amplifier comprising a first input, a second input, and a first output, wherein the amplifier is configured to generate an output signal indicative of an error between an output reference signal and an internal reference signal. The reference buffer further includes a first voltage follower circuit configured to generate the output reference signal based, at least in part, on the output signal of the error amplifier, wherein the first voltage follower comprises a third input and a second output, and wherein the second output is coupled to the second input of the error amplifier.

Abstract: A process for preparing isopropanol by hydrogenating acetone includes the steps of (1) introducing an acetone raw material into an acetone pre-oxidation processor to preoxidize impurities to obtain a pre-oxidized acetone raw material; and (2) introducing the acetone raw material after the pre-oxidation treatment and an optional intermediate treatment into an acetone hydrogenation reactor to conduct a hydrogenation reaction to obtain a crude isopropanol product.

Abstract: The invention provides a transcription factor PfAP2-O5 inhibitor for Plasmodium falciparum, a pharmaceutical composition, and a drug for treating malaria resistant to artemisinin and an analog thereof. Disclosed in the present invention is new use of a triazoloquinoline derivative or a pharmaceutically acceptable salt or hydrate thereof. The triazoloquinoline derivative can inhibit the expression of an invasion gene pfap2-o5, block the invasion of Plasmodium falciparum into red blood cells, affect its growth and development, and achieve the effect of killing Plasmodium falciparum. Therefore, the triazoloquinoline derivative can be used as an inhibitor for pfap2-o5, a drug for inhibiting Plasmodium falciparum, or a drug for preventing or treating malaria.

Abstract: Embodiments of the present disclosure provide a secure channel sleep wake-up method, apparatus and device. The method comprises: when a node 1 is awakened from a sleep state, obtaining stored IP communication information communicating with a node 2, performing message encapsulation by using the IP communication information to obtain a first message, and sending the first message to the node 2; the node 2 obtaining the IP communication information and a key updating request message from the first message, and generating a second key according to information comprising a basic key corresponding to a basic key identifier in the key updating request message and a first random number generated by the node 1 and in combination with a second random number self-generated by the node 2; the node 1 obtaining the IP communication information and a key updating response message, and generating the second key and the second random number.

Abstract: A metal oxygen-containing complex has a transition metal element as central atom and an oxygen-containing heterocyclic organic compound containing a substituent as ligand. The ligand is a compound having a structure of formula (I).

Abstract: The invention provides a transcription factor PfAP2-O5 inhibitor for Plasmodium falciparum, a pharmaceutical composition, and a drug for treating malaria resistant to artemisinin and an analog thereof. Disclosed in the present invention is new use of a hexahydroquinoline derivative or a pharmaceutically acceptable salt or hydrate thereof. The hexahydroquinoline derivative can inhibit the expression of an invasion gene pfap2-o5, block the invasion of Plasmodium falciparum into red blood cells, affect its growth and development, and achieve the effect of killing Plasmodium falciparum. Therefore, the hexahydroquinoline derivative can be used as an inhibitor for pfap2-o5, a drug for inhibiting Plasmodium falciparum, or a drug for preventing or treating malaria.

Abstract: Disclosed is an identity authentication method. During the process of a requesting device authenticating the identity of an authentication access controller, confidentiality processing is performed on identity information that carries private and sensitive information, and identity authentication result information, thus private and sensitive information can be prevented from being exposed, such that an attacker cannot acquire private and sensitive information in a first authentication response message or an authentication result message even if they have intercepted same, thereby preventing an attack of an attacker on a legitimate authentication access controller, and ensuring the security of the authentication access controller, the requesting device and even a network. Further disclosed are an identity authentication apparatus, a storage medium, a program, and a program product.

Abstract: The technology of this application relates to a pose determining method. The method includes obtaining a first image, when first pose information determined based on the first image meets a pose anomaly condition, displaying prompt information for indicating to photograph a target object, and obtaining, by using the target object in the target image captured by a user based on the prompt, second pose information that does not meet the pose anomaly condition. When high-precision pose information cannot be determined, pose positioning is implemented by using the target object in a scenario. In addition, in a process of determining pose information of a terminal device, prompt information for indicating the user to photograph the target object is displayed, and the user is indicated to photograph the target object, thereby avoiding that the user does not know how to operate or scan an invalid target object.

Abstract: A clock calibrator comprises an input port configured to receive a two-level symbol from a quarter-rate transmitter, the two-level symbol having a period of P unit intervals with a first rising edge launched by one quarter-rate clocks. The clock calibrator includes a clock generator configured to generate four calibration clocks based on the quarter-rate clocks, each calibration clock having the period of P UIs and sequentially having a calibration rising edge delayed by M UIs. The clock calibrator includes a delay-tuner configured to retime the calibration rising edge and a phase detector configured to determine a coarse parameter and a k-th fine parameter based on alignment between the retimed calibration rising edge and the first rising edge with (k?1)M UIs delay. Here P is an integer multiple of 4, M is one less than an integer multiple of 4, and k is selected from 1, 2, 3, and 4.

Abstract: An example phase interpolator in an integrated circuit (IC) includes: a first circuit including a transistor pair and a current source, the transistor pair including a first transistor coupled between a first node and the current source, and second transistor coupled between a second node and the current source, a gate of the first transistor configured to receive a first clock signal and a gate of the second transistor configured to receive a second clock signal that is antiphase with the first clock signal; a load circuit including a first inductor coupled between the first node and the second node and a resistor coupled between a voltage source and a center terminal of the first inductor; and a second circuit coupled between the center terminal of the first inductor and an alternating current (AC) ground, the second circuit tuned to conduct a second harmonic of the first clock signal.

Abstract: An example amplifier includes a first transconductance circuit, which includes a first output coupled to a first current source, a first input, a first network, and a cascode circuit; and a second transconductance circuit, which includes a second output coupled to a second input and a second current source; wherein the first current source is coupled to a supply voltage and the second current source is coupled to an electrical ground; and wherein the first output is coupled to the second output.

Abstract: A visual localization method includes obtaining an image captured by a terminal device; obtaining two-dimensional line feature information of the image that includes at least one of information about a boundary between a building and a non-building or information about a boundary between a non-building and a non-building; and determining a localization pose of the terminal device based on location information of the terminal device, magnetometer angle deflection information of the terminal device, a satellite map, and the two-dimensional line feature information.

Abstract: Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). The SAR ADC includes a sample and digital to analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the sample and DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits. The first set of storage circuits are coupled to the comparator circuit and the sample and DAC circuit. The comparator driver can include a first driver and second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to first inputs of a second set of storage circuits within the first set of storage circuits.

Abstract: An example data path to a receiver includes: an analog front-end circuit (AFE) configured to receive a first voltage supply; a first circuit coupled to an output of the AFE, the first circuit including: a first buffer having an input coupled to the output of the AFE; a second buffer; a first switch coupled between an output of the first buffer and an input of the second buffer; and a second switch coupled between an output of the second buffer and an input of an ADC of the receiver; wherein the first buffer is configured to receive the first voltage supply, the second buffer is configured to receive a second voltage supply, and the ADC is configured to receive a third voltage supply less than the first voltage supply.

Abstract: A fascia gun includes a housing, a movement assembly, a massage head and a conduction component. When the massage head is separated from the piston, the trigger and the switch controller are spaced apart from each other, and the switch controller is configured to disconnect the anti-mistouch circuit of the main control board to limit the main control board from controlling the start of the driver. When the massage head is connected to the piston, the trigger is configured to trigger the switch controller to conduct the anti-mistouch circuit of the main control board to release the restriction of the main control board on the driver.

Abstract: This application provides a centrifugal compressor and a refrigeration heat pump unit, the centrifugal compressor includes a first compression chamber including a first inlet portion that includes a first variable guide vane, and a first outlet portion. A second compression chamber including a second inlet portion that includes a second variable guide vane, and a second outlet portion. A first impeller rotatably disposed inside the first compression chamber and disposed adjacent to the first variable guide vane. A second impeller rotatably disposed inside the second compression chamber and disposed adjacent to the second variable guide vane. A third impeller rotatably disposed inside the first compression chamber and located downstream of the first impeller. A first bypass pipe allowing a discharge flow passage of the third impeller to communicate with an inlet of the third impeller.