Abstract: A device may include an oscillator and a driver. The oscillator may be coupled to circuitry providing calibration of the oscillator. The oscillator may receive from the circuitry a first signal that causes the oscillator to generate a second signal having a first frequency to be used for calibration of an analog-to-digital converter (ADC). The driver may be coupled to the oscillator and the ADC. The driver may receive the second signal from the oscillator. The driver may receive a third signal indicating an amplitude to apply to the second signal. The driver may provide, to the ADC based at least on the second signal and the third signal, an output signal having the first frequency and the amplitude.

Abstract: An apparatus including a comparator and a plurality of replica current sources. The comparator outputs a control voltage onto an output line upon comparing a midpoint voltage with a feedback voltage. The control voltage indicates whether the feedback voltage is higher or lower than the midpoint voltage. Each of the replica current sources draws a supply voltage from a supply line. A replica current source enters into an inactive state in response to an enable signal being in a deactivating state. Upon entering the inactive state, the replica current source ceases drawing the control voltage from the output line.

Abstract: Various systems and methods for implementing LiDAR-based object tracking described herein. An object tracking system for a vehicle includes an interface to communicate with object detection circuitry and an object similarity calculator circuitry, to obtain segmented data of an environment the object tracking system is operating within, the segmented data obtained using a light imaging detection and ranging (LiDAR) system, and the segmented data including a first plurality of segments detected in a first frame and a second plurality of segments detected in a second frame, the second frame captured after the first frame; determine, for a given segment of the first plurality of segments, a similar segment in the second plurality of segments; assign an VEHICLE object identification of the given segment to the similar segment; and track the similar segment from the first frame to the second frame based on the object identification.

Abstract: An apparatus includes a first phase interpolator configured to receive a first clock signal and generate a second clock signal, and an ADC that includes a clock divider configured to generate a third clock signals based on the second clock signal, a token generator configured to generate a first token signal, a first phase detector configured to generate a first and second output based on the first and third clock signals, and a second phase detector configured to generate a third output based on the token signal. Control logic may be provided to perform a foreground calibration to align the first token signal with a second token signal of a second ADC-group, and a background calibration to align the third clock signal with the first clock signal.

Abstract: Described herein are systems and methods related to a device including an analog-to-digital converter (DAC) configured to convert a digital signal into an analog signal. The systems and methods can receive an analog signal at a first input, and provide the analog signal to a first output in response to a first clock signal. The first clock signal has a level at least partially dependent on the analog signal. The systems and methods can provide a path to a ground node for the first clock signal in response to a second clock signal. The second clock signal is independent of the analog signal.

Abstract: A circuit including a first resistor, a second resistor, a current source and a transistor. The first resistor is between a voltage rail and a drive interconnect. The drive interconnect and the voltage rail are electrically connected to the first resistor. The second resistor is between the drive interconnect and ground. Ground and the drive interconnect are electrically connected to the second resistor. The current source is between the voltage rail and the drive interconnect. The drive interconnect and the voltage rail are electrically connected to the current source. The transistor is between the drive interconnect and a sink interconnect. The drive interconnect and the sink interconnect are electrically connected to the transistor.

Abstract: A system may include one or more receivers, circuitry, and a controller. Each of the one or more receivers may include a plurality of analog-to-digital converters (ADCs). Each ADC may measure a time relating to an analog-to-digital conversion by the ADC, compare the time with a threshold, and generate, based on a result of the comparing, a first signal. The circuitry may be coupled to the one or more receivers. The circuitry may receive the first signal from each ADC, determine, based at least on the first signal, characteristics of performance of each receiver, and output a plurality of second signals. Each of the plurality of second signals may indicate the characteristics of performance of a corresponding receiver. The controller may be coupled to the circuitry and adjust a voltage provided to the one or more receivers, based at least on the plurality of second signals received from the circuitry.

Abstract: The subject technology is directed to clock calibration systems and methods. In an embodiment, the subject technology provides an apparatus for clock calibration to minimize timing discrepancies between even and odd clock edges. The apparatus includes a first data path configured to generate a first signal, the first signal comprising a first edge and a second edge associated with even and odd clock cycles, respectively. A calibration circuit is coupled to the first data path and configured to determine a timing difference between the first edge and the second edge to calculate even-odd jitter (EOJ). This configuration enables precise calibration to reduce EOJ and ensure accurate synchronization of clock signals in high-speed communication systems.

Abstract: A power supply circuit board is provided with a step-down converter and a power input port, and the step-down converter is electrically connected to the power input port. The power input port is configured to receive an input voltage, and the step-down converter is configured to convert the input voltage into a voltage required by a chip component. The power supply circuit board is further provided with a first connector, and the first connector is electrically connected to the step-down converter. The first connector mates with a second connector of a voltage regulator in the chip component, the first connector is disposed opposite to the second connector, and the chip component obtains, through the first connector, the voltage required by the chip component.

Abstract: An apparatus for canceling clock-to-signal interference in a multi-lane SerDes comprising an analog front-end circuit receiving an input signal from a signal path mixed with interference from a clock path. The apparatus includes a phase interpolator circuit implemented in the clock path to generate multiple phases of a clock signal and to provide a timing rotated by the phases for a track-and-hold circuit to sample the input signal and the interference in every cycle. The apparatus also includes an analog-to-digital converter configured to digitize the input signal and the interference to provide an ADC output and a digital-interference-cancellation circuit configured to demultiplex the ADC output and detect a baseline offset associated with the interference sampled at one of the phases in each demultiplexed path using a digital loop to calibrate the baseline offset.

Abstract: A fog collecting box and a bubble machine are provided. The fog collecting box is mounted in the bubble machine. The fog collecting box includes an inlet, an outlet, and a channel defined in the fog collecting box. The channel is communicated between the inlet and the outlet of the fog collecting box. The channel includes at least one bending section, so that a length of the channel is greater than a linear distance between the inlet and the outlet of the fog collecting box.

Abstract: A reference buffer with wide output voltage and current range is provided. A reference buffer includes an error amplifier comprising a first input, a second input, and a first output, wherein the amplifier is configured to generate an output signal indicative of an error between an output reference signal and an internal reference signal. The reference buffer further includes a first voltage follower circuit configured to generate the output reference signal based, at least in part, on the output signal of the error amplifier, wherein the first voltage follower comprises a third input and a second output, and wherein the second output is coupled to the second input of the error amplifier.

Abstract: A process for preparing isopropanol by hydrogenating acetone includes the steps of (1) introducing an acetone raw material into an acetone pre-oxidation processor to preoxidize impurities to obtain a pre-oxidized acetone raw material; and (2) introducing the acetone raw material after the pre-oxidation treatment and an optional intermediate treatment into an acetone hydrogenation reactor to conduct a hydrogenation reaction to obtain a crude isopropanol product.

Abstract: The invention provides a transcription factor PfAP2-O5 inhibitor for Plasmodium falciparum, a pharmaceutical composition, and a drug for treating malaria resistant to artemisinin and an analog thereof. Disclosed in the present invention is new use of a triazoloquinoline derivative or a pharmaceutically acceptable salt or hydrate thereof. The triazoloquinoline derivative can inhibit the expression of an invasion gene pfap2-o5, block the invasion of Plasmodium falciparum into red blood cells, affect its growth and development, and achieve the effect of killing Plasmodium falciparum. Therefore, the triazoloquinoline derivative can be used as an inhibitor for pfap2-o5, a drug for inhibiting Plasmodium falciparum, or a drug for preventing or treating malaria.

Abstract: Embodiments of the present disclosure provide a secure channel sleep wake-up method, apparatus and device. The method comprises: when a node 1 is awakened from a sleep state, obtaining stored IP communication information communicating with a node 2, performing message encapsulation by using the IP communication information to obtain a first message, and sending the first message to the node 2; the node 2 obtaining the IP communication information and a key updating request message from the first message, and generating a second key according to information comprising a basic key corresponding to a basic key identifier in the key updating request message and a first random number generated by the node 1 and in combination with a second random number self-generated by the node 2; the node 1 obtaining the IP communication information and a key updating response message, and generating the second key and the second random number.

Abstract: A metal oxygen-containing complex has a transition metal element as central atom and an oxygen-containing heterocyclic organic compound containing a substituent as ligand. The ligand is a compound having a structure of formula (I).

Abstract: The invention provides a transcription factor PfAP2-O5 inhibitor for Plasmodium falciparum, a pharmaceutical composition, and a drug for treating malaria resistant to artemisinin and an analog thereof. Disclosed in the present invention is new use of a hexahydroquinoline derivative or a pharmaceutically acceptable salt or hydrate thereof. The hexahydroquinoline derivative can inhibit the expression of an invasion gene pfap2-o5, block the invasion of Plasmodium falciparum into red blood cells, affect its growth and development, and achieve the effect of killing Plasmodium falciparum. Therefore, the hexahydroquinoline derivative can be used as an inhibitor for pfap2-o5, a drug for inhibiting Plasmodium falciparum, or a drug for preventing or treating malaria.

Abstract: Disclosed is an identity authentication method. During the process of a requesting device authenticating the identity of an authentication access controller, confidentiality processing is performed on identity information that carries private and sensitive information, and identity authentication result information, thus private and sensitive information can be prevented from being exposed, such that an attacker cannot acquire private and sensitive information in a first authentication response message or an authentication result message even if they have intercepted same, thereby preventing an attack of an attacker on a legitimate authentication access controller, and ensuring the security of the authentication access controller, the requesting device and even a network. Further disclosed are an identity authentication apparatus, a storage medium, a program, and a program product.

Abstract: The technology of this application relates to a pose determining method. The method includes obtaining a first image, when first pose information determined based on the first image meets a pose anomaly condition, displaying prompt information for indicating to photograph a target object, and obtaining, by using the target object in the target image captured by a user based on the prompt, second pose information that does not meet the pose anomaly condition. When high-precision pose information cannot be determined, pose positioning is implemented by using the target object in a scenario. In addition, in a process of determining pose information of a terminal device, prompt information for indicating the user to photograph the target object is displayed, and the user is indicated to photograph the target object, thereby avoiding that the user does not know how to operate or scan an invalid target object.

Abstract: A clock calibrator comprises an input port configured to receive a two-level symbol from a quarter-rate transmitter, the two-level symbol having a period of P unit intervals with a first rising edge launched by one quarter-rate clocks. The clock calibrator includes a clock generator configured to generate four calibration clocks based on the quarter-rate clocks, each calibration clock having the period of P UIs and sequentially having a calibration rising edge delayed by M UIs. The clock calibrator includes a delay-tuner configured to retime the calibration rising edge and a phase detector configured to determine a coarse parameter and a k-th fine parameter based on alignment between the retimed calibration rising edge and the first rising edge with (k?1)M UIs delay. Here P is an integer multiple of 4, M is one less than an integer multiple of 4, and k is selected from 1, 2, 3, and 4.