Abstract: Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). The SAR ADC includes a sample and digital to analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the sample and DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits (e.g., ratioed latched. The first set of storage circuits are coupled to the comparator circuit and the sample and DAC circuit. The comparator driver can include a first driver and second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to first inputs of a second set of storage circuits within the first set of storage circuits.

Abstract: An identity authentication method is disclosed in embodiments of the present application. When a requester and an authentication access controller perform identity authentication using an authentication mechanism of a pre-shared key, the identity information of entities is transmitted in the form of ciphertext, thereby preventing the identity information of the entities from being exposed during the transmission, so that attackers cannot obtain private or sensitive information. The mutual or unilateral identity authentication between the authentication access controller and the requester is achieved while ensuring the confidentiality of the entity identity and related information, thereby laying a foundation for ensuring that the user accessing the network is legitimate and/or the network accessed by the user is legitimate.

Abstract: Provided is a system and method for dynamic configuration of a multi-objective optimization function and identifying an optimal set of records based thereon. In one example, the method may include receiving a set of data records and priority values to be applied to the set of data records, generating an objective function from an objective function template stored in a memory device, wherein the generating comprises dynamically configuring parameter values of the objective function based on the priority values, executing the objective function on the set of data records and identifying an optimal subset of data records from among the set of data records based on the dynamically configured parameter values of the executing objective function, and displaying identifiers of the identified optimal subset of data records.

Abstract: The present disclosure relates to the technical field of alien invasive species control, in particular to use of 4-nitro-3-(trifluoromethyl)phenol in killing or controlling Pomacea canaliculata, a method for killing or controlling the Pomacea canaliculata, and a molluscicide. The present disclosure provides use of 4-nitro-3-(trifluoromethyl)phenol in killing or controlling Pomacea canaliculata. The 4-nitro-3-(trifluoromethyl)phenol can effectively control the Pomacea canaliculata with a low cost. In the present disclosure, the results of examples show that: the 4-nitro-3-(trifluoromethyl)phenol has an obvious killing effect on the Pomacea canaliculata, showing a control effect comparable to that of niclosamide, a commonly-used molluscicide for killing the Pomacea canaliculata.

Abstract: Embodiments of this application disclose a head-mounted wireless headset and a communication method thereof, and relate to the communication field. A specific solution is as follows: The head-mounted wireless headset includes: a first headphone, including: a first short-range wireless communication chip and a first radio frequency antenna, where the first short-range wireless communication chip is coupled to the first radio frequency antenna; a second headphone, including: a second short-range wireless communication chip and a second radio frequency antenna, where the second short-range wireless communication chip is coupled to the second radio frequency antenna; and a data bus, separately connected to the first short-range wireless communication chip and the second short-range wireless communication chip, and configured to provide a physical link required for communication between the first short-range wireless communication chip and the second short-range wireless communication chip.

Abstract: The present disclosure provides a method and a device for preparing a modified poly (m-phenylene isophthalamide) (PMIA) fiber by continuous polymerization-dry-wet spinning. The method includes the following steps: (1) preparing a mixed solution of m-phenylenediamine (MPD) and a copolymerized diamine monomer in N,N-dimethylacetamide (DMAC) serving as a solvent using a cosolvent; (2) mixing isophthaloyl chloride (IPC) with the mixed solution of the MPD and the copolymerized diamine monomer in the DMAC, and conducting pre-polycondensation and polycondensation in sequence to obtain a modified PMIA resin solution; and (3) subjecting the modified PMIA resin solution to additive addition, filtration, defoaming, and dry-wet spinning to obtain the modified PMIA fiber.

Abstract: The present disclosure provides a blending method of high-quality and dual-purpose flour for bread and noodles, belonging to the technical field of flour processing. The method includes: selecting flour of a high-quality and dual-purpose wheat variety for bread and noodles as a high-quality basic flour for blending; according to a large gradient experimental design, selecting a gradient range ratio with a sedimentation value ?46.0 mL and a dough development time ?9.6 min, followed by subdividing for small gradient experiments; selecting a ratio with flour sedimentation value and dough development time that reach an ideal value to blend a large amount of flour; and making bread and noodles for scoring, followed by determining a blending ratio if a scoring result reaches an ideal value.

Abstract: The sense amplifier includes: an amplification module configured to amplify a voltage transmitted by a bit line or a reference bit line, when the sense amplifier is at an amplification stage; a first switch module configured to control the amplification module to be disconnected from the reference bit line, when the sense amplifier performs a read operation for the bit line and is at the amplification stage. In the disclosure, the power consumption of the sense amplifier may be reduced.

Abstract: A sense amplifier, a memory and a method for controlling the sense amplifier are provided. The sense amplifier includes: an amplification module, arranged to read data in a memory cell; and a control module, electrically connected to the amplification module. In a first offset compensation stage of the sense amplifier, the control module is arranged to configure the amplification module to include a first inverter and a second inverter, and each of the first inverter and the second inverter is an inverter an input terminal and an output terminal connected to each other; and in a second offset compensation stage of the sense amplifier, the control module is arranged to configure the amplification module to include a current mirror structure.

Abstract: The disclosure provides a Sense Amplifier (SA), a memory and a method for controlling the SA, and relates to the technical field of semiconductor memories. The SA includes: an amplifier module; an offset voltage storage unit electrically connected to the amplifier module and configured to store an offset voltage of the amplifier module in an offset elimination stage of the SA; and a load compensation unit electrically connected to the amplifier module and configured to compensate a difference between loads of the amplifier module in an amplification stage of the SA. The disclosure may improve an accuracy of reading data of the SA.

Abstract: The present disclosure discloses a method for synthesizing high-quality magnetic resonance images, wherein the method expands the value ranges of echo time TE and repetition time TR in a magnetic resonance signal formula to negative intervals, and expands the contribution of proton density PD to a negative power. The method can effectively reduce the influence of the measurement error of quantitative magnetic resonance imaging tissue parameters on the tissue contrast of the synthetic magnetic resonance image, and can obviously improve the tissue contrast of the synthetic magnetic resonance image. This method will significantly improve the imaging quality of synthetic magnetic resonance imaging, and promote its detection effect in neuroscience and clinical lesions. This method is expected to improve the imaging quality of synthetic magnetic resonance imaging and promote its detection effect in neuroscience and clinical lesions.

Abstract: Disclosed herein are related to systems and methods for a successive approximation analog to digital converter (SAR ADC). In one aspect, the SAR ADC includes a calibration circuit configured to receive some or all of the plurality of bits corresponding to the input voltage and accumulates or averages at least some of the bits corresponding to the input voltage. The calibration circuit is configured to provide a first offset signal to control a first offset associated with a first comparator, a second offset signal to control a second offset associated with a second comparator, or reduce an offset difference associated with the first offset and the second offset.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a network node may transmit, and a user equipment (UE) may receive, signaling that indicates at least a first random access channel (RACH) occasion (RO) partition and a second RO partition. The first RO partition may be associated with different uplink transmission capabilities than the second RO partition. The UE may select an RO in the first RO partition or the second RO partition based at least in part on a metric that relates to an uplink transmission capability of the UE. The UE may transmit, and the network node may receive, a preamble in the selected RO to initiate a RACH procedure. Numerous other aspects are described.

Abstract: A security defending method, a coprocessor, and a processing apparatus are disclosed. The security defending method is applicable in a coprocessor, including: receiving a jump destination encryption request for the operation task; using mask configuration to perform first mask processing on the first jump destination address value to obtain a first intermediate jump destination address value; performing an authentication operation based on the first jump destination storage address, a key reference value corresponding to the operation task and the first intermediate jump destination address value, to obtain a first encryption result value; using the mask configuration to perform second mask processing on the first encryption result value to obtain a first intermediate encryption result value; performing an authentication operation on the first intermediate encryption result value and the first jump destination address value to obtain a first encryption jump destination address value.

Abstract: A security defending method and an electronic apparatus are disclosed. The security defending method is applicable in a coprocessor, including: receiving a jump destination encryption request for the operation task; using mask configuration to perform first mask processing on the first jump destination address value to obtain a first intermediate jump destination address value; performing an authentication operation based on the first jump destination storage address, a key reference value corresponding to the operation task and the first intermediate jump destination address value, to obtain a first encryption result value; using the mask configuration to perform second mask processing on the first encryption result value to obtain a first intermediate encryption result value; performing an authentication operation on the first intermediate encryption result value and the first jump destination address value to obtain a first encryption jump destination address value.

Abstract: A device is provided that includes a counter circuit configured to count cycles of an input clock signal and to generate an output clock signal periodically based on a cycle count of the input clock signal; a multi-phase clock generator configured to generate a plurality of multi-phase clock signals from a system clock signal; a multiplexer circuit coupled to the multi-phase clock generator and configured to provide a multi-phase clock signal selected from the plurality of multi-phase clock signals to the counter circuit as the input clock signal; and a selection circuit configured to provide a selection signal to the multiplexer circuit periodically to switch the multi-phase clock signal provided to the counter circuit from a current multi-phase clock signal to a next multi-phase clock signal selected from the plurality of multi-phase clock signals.

Abstract: An apparatus may include a first clock generator configured to receive an input clock signal, and generate two or more first-level clock signals of a track-and-hold circuit, a phase interpolator configured to generate an interpolated clock signals, wherein the interpolated clock signal is based on the two or more first-level clock signals, and a second clock generator configured to generate two or more second-level clock signals based on the interpolated clock signal, wherein the phase of the two or more second-level clock signals relative to the phase of a respective first-level clock signal is determined, at least in part, by the phase of the interpolated clock signal.

Abstract: Disclosed is an identity authentication method. During the process of a requesting device authenticating the identity of an authentication access controller, confidentiality processing is performed on identity information that carries private and sensitive information, and identity authentication result information, thus private and sensitive information can be prevented from being exposed, such that an attacker cannot acquire private and sensitive information in a first authentication response message or an authentication result message even if they have intercepted same, thereby preventing an attack of an attacker on a legitimate authentication access controller, and ensuring the security of the authentication access controller, the requesting device and even a network. Further disclosed are an identity authentication apparatus, a storage medium, a program, and a program product.

Abstract: An identity authentication method and apparatus, a device, a chip, a storage medium, and a program. Confidentiality processing is performed on identity information of a requesting device and an authentication access controller, such that the identity information of the requesting device and the authentication access controller is prevented from being exposed during a transmission process, thereby ensuring that an attacker cannot obtain private and sensitive information of the requesting device and the authentication access controller. In addition, by means of involving an authentication server, mutual identity authentication of the requesting device and the authentication access controller is realized while the confidentiality of information related to an entity identity is ensured.

Abstract: Disclosed in the present application are an identity authentication method and apparatus, and a device, a chip, a storage medium and a program. The identity information of a requesting device is confidentially processed to prevent the identity information of the requesting device from being exposed during transmission, thereby ensuring that an attacker cannot obtain the private information of the requesting device. In addition, by introducing an authentication server, real-time two-way identity authentication between the requesting device and an authentication access controller is achieved while ensuring the confidentiality of entity identity-related information.