Abstract: A blank mask includes a pattern target layer formed over a transparent substrate and a self-assembly monolayer disposed over and modifying the surface of a back side of the transparent substrate opposite to the pattern target layer.

Abstract: Provided is a method of changing an output current value of an off-chip driver by means of a counting circuit including pluralities of fuses for controlling the off-chip driver, that includes measuring the output current value of the off-chip driver after completing a wafer test; cutting the fuses of the counting circuit off when the measured output current value is smaller than a target value, increasing the initial value of a off-chip driving control signal; and fabricating a package when the measured output current value is equal to a target value.

Abstract: A semiconductor memory apparatus which can restrict a refresh operation for a period when an internal clock is synchronized with an external clock. The semiconductor memory apparatus includes a refresh control unit that disables a refresh command signal which is applied during a period when an enable signal is enabled but a lock-completion signal is not enabled in response to the enable signal outputted from a mode register, the lock-completion signal outputted from a clock synchronizing unit, and the refresh command signal outputted from a command decoder. The clock synchronizing unit can stably complete a locking operation within a predetermined time regardless of power-supply noise and so on.

Abstract: A semiconductor memory device in which only global I/O buses, which receive one or more data groups that must be output first among a N number of data groups that are prefetched in a N-bit prefetch type, from an array of memory cells are precharged with a ½ power supply voltage, thereby making the output speed of the data groups that must be output first thing faster than that of the remaining data groups. The semiconductor memory device includes a data bus controller for precharging predetermined data buses that receive one or more data group that must be output to the outside first among a N number of data groups that are prefetched in a N-bit prefetch type from an array of memory cells, using information to decide an I/O sequence of the N number of the data groups.

Abstract: Provided is a counting circuit for controlling an off-chip driver and method of changing a DC output current value of the off-chip driver using the same in accordance with variations of processing characteristics with PMOS and NMOS in the state of wafer level. The counting circuit for controlling the off-chip driver includes: pluralities of latch circuits counting to generate pluralities of off-chip driving control signals; pluralities of fuse blocks generating set and reset input signals to vary initial values of the off-chip driving control signals; and pluralities of initial value modifying circuit varying the initial value of the off-chip driving control signals in response to the set and reset input signals.

Abstract: A synchronous semiconductor memory device reduces operation current by limiting unnecessary internal operations with a command interval defined in JEDEC Standard. The synchronous semiconductor memory device comprises a clock buffer, a plurality of command, a plurality of address buffers, a command decoder, a clock driving unit and a plurality of address latches. Here, the command decoder generates an internal command in response to output signals from the plurality of command buffers synchronously with respect to an internal clock. The clock driving unit drives a clock outputted from the clock buffer to generate the internal clock, and generates a latch clock that toggles only when the internal command is generated. The plurality of address latches generate a plurality of latch addresses in response to a plurality of internal addresses outputted from the plurality of address buffers synchronously with respect to the latch clock.

Abstract: In a substantially planar circuit, the conductors are separated by an inorganic material with a dielectric constant of less than about 3.0. The dielectric layers are formed in a process that includes defining trenches and/or vias for the conductors by imprinting an initially planar layer of a radiation curable composition. The imprinting die is preferably UV transparent such that the composition is UV cured while the imprint die is in place. The curable composition includes an organic modified silicate compound and a second decomposable organic component, the latter forming nanometer scale pores as the organic compounds are subsequently decomposed to provide a polysilicate matrix. The pores reduce the effective dielectric constant from that of otherwise dense silicon dioxide.

Abstract: Disclosed is an address buffer circuit for a memory device, the address buffer circuit comprising: a first address input buffer group and a second address input buffer group for receiving an address signal applied from the exterior; and a control unit for controlling operation of the second address input buffer group. Herein, operation of the first address input buffer group is controlled by a first control signal, and the control unit receives a second control signal enabled when all banks of the memory device enter an active state and controls operation of the second address input buffer group.

Abstract: Disclosed is a delay locked loop (DLL) circuit. The DLL circuit detects a frequency of an external clock signal and adjusts a coarse delay during a DLL circuit operation, thereby quickly terminating a feedback operation of the DLL circuit and having a reduced circuit area of a delay line. Therefore, the DLL circuit can be used for next generation high-integration and high-frequency memory devices such as DDR2 SDRAMs.

Abstract: A clock duty ratio correction circuit corrects a duty ratio of internal clock signals at 1:1. The clock duty ratio correction circuit comprises a clock buffer unit, a charge pump unit, a comparison control unit, a voltage comparison unit, a counter and a D/A converter. The clock duty ratio correction circuit converts a differential internal clock signal into a voltage level corresponding to the pulse width of the differential internal clock signal, and compares the voltage level to generate a count signal. Additionally, the clock duty ratio correction circuit divides a reference voltage at a predetermined ratio in response to the count signal to generate a duty ratio correcting signal, and corrects the duty ratio of the differential internal clock signal by using the voltage level difference of the duty ratio correcting signal.

Abstract: A semiconductor package comprising a die pad defining opposed top and bottom surfaces and a peripheral edge. Attached to the peripheral edge of the die pad is a plurality of support feet which extend downwardly relative to the bottom surface thereof. A plurality of leads extend at least partially about the peripheral edge of the die pad in spaced relation thereto. Attached to the top surface of the die pad is a semiconductor die which is electrically connected to at least one of the leads. A package body encapsulates the die pad, the support feet, the leads and the semiconductor die such that at least portions of the leads are exposed in the package body.

Abstract: A refrigeration system regulates the temperature of an electrostatic wafer chuck disposed in a process chamber. The refrigeration system includes a heat exchanger disposed in a heat exchange relationship with the electrostatic chuck, a refrigerator, a temperature sensor, and a temperature controller for controlling the refrigerator to cool the coolant withdrawn from the heat exchanger to a desired temperature in response to the temperature detected by the temperature sensor. The heat exchanger forms a coolant passageway inside the electrostatic chuck, and the refrigerator is disposed outside the process chamber. The temperature sensor is disposed within the body of the electrostatic chuck. The temperature of the electrostatic chuck can be regulated so as to be maintained nearly constant because the temperature used to control the cooling of the coolant is measured directly from the body of the electrostatic chuck.

Abstract: A refrigeration system regulates the temperature of an electrostatic wafer chuck disposed in a process chamber. The refrigeration system includes a heat exchanger disposed in a heat exchange relationship with the electrostatic chuck, a refrigerator, a temperature sensor, and a temperature controller for controlling the refrigerator to cool the coolant withdrawn from the heat exchanger to a desired temperature in response to the temperature detected by the temperature sensor. The heat exchanger forms a coolant passageway inside the electrostatic chuck, and the refrigerator is disposed outside the process chamber The temperature sensor is disposed within the body of the electrostatic chuck. The temperature of the electrostatic chuck can be regulated so as to be maintained nearly constant because the temperature used to control the cooling of the coolant is measured directly from the body of the electrostatic chuck.

Abstract: An apparatus for manufacturing a semiconductor device having a stage for loading a wafer includes: a flat horizontal main surface formed so that the wafer can be fully seated thereon; a perimeter surface formed at an outer portion of the stage and spaced at a predetermined distance from the flat main surface at a height lower than that of the flat main surface; and an annular slope formed between an outer circumference of the flat main surface and an inner circumference of the perimeter surface. The annular slope has a predetermined angle of inclination with respect to the flat main surface. The apparatus prevents the occurrence of plasma buildup and minimizes poor processing uniformity due to the buildup of polymer deposits on the stage.