Patents by Inventor Jun Etoh
Jun Etoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5579256Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.Type: GrantFiled: May 31, 1995Date of Patent: November 26, 1996Assignee: Hitachi, Ltd.Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
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Patent number: 5539279Abstract: A highly reliable and high speed ferroelectric memory having a high degree of integration. In a ferroelectric memory having a multiple of memory cells M1, each constituted by one transistor and one ferroelectric capacitor, in the normal operation, the ferroelectric memory is used as a volatile memory in which a voltage on a storage node ST1 stores information in a DRAM mode. Both the electric potential at the plate PL1 of the ferroelectric capacitor and a precharge electric potential on a data line DL1(j) are Vcc/2. When the a power supply voltage is turned on, a polarization state is detected as a ferroelectric memory of a plate electric potential of Vcc/2 and a precharge electric potential of Vss (or Vcc) and the read operation is performed a FERAM mode.Type: GrantFiled: December 22, 1994Date of Patent: July 23, 1996Assignee: Hitachi, Ltd.Inventors: Kan Takeuchi, Masashi Horiguchi, Masakazu Aoki, Katsumi Matsuno, Takeshi Sakata, Jun Etoh, Yoshinobu Nakagome
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Patent number: 5526313Abstract: Disclosed is a one-chip ULSI which can carry out the fixed operation in a wide range of power supply voltage (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which serves to a fixed internal voltage for a wide range of power supply voltage, an input/output buffer which can be adapted to several input/output levels, a dynamid RAM(s) which can operate at a power supply voltage of 2 V or less, etc. This one-chip ULSI can be applied to compact and portable electronic devices such as a lap-top type personal computer, an electronic pocket note book, a solid-state camera, etc.Type: GrantFiled: August 10, 1993Date of Patent: June 11, 1996Assignees: Hitachi Ltd., Hitachi VLSI Engineering CorporationInventors: Jun Etoh, Kiyoo Itoh, Yoshiki Kawajiri, Yoshinobu Nakagome, Eiji Kume, Hitoshi Tanaka
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Patent number: 5467314Abstract: In an address multiplexed dynamic random access memory (RAM) which has both a normal operation mode and a test mode capability, the test mode is initiated in response to particular signal level combinations of both the row address strobe (RAS) and column address strobe (CAS) signals and the write enable (WE) signal. Since the signal level combinations employed in connection with implementing the test mode are unused in the normal operating mode of the dynamic RAM, additional external terminals are unneeded. This dynamic RAM employs multiplexing circuitry on both the input side as well as on the output side of the dynamic RAM, which multiplexing circuitry is controlled during normal operation by select signals from a decoder and during the test mode by a test signal which allows accessing of data at all of the common complementary data lines by the testing circuitry so as to determine whether there is consistency or inconsistency of the data being read out for testing.Type: GrantFiled: July 18, 1994Date of Patent: November 14, 1995Assignee: Hitachi, Ltd.Inventors: Kazuyuki Miyazawa, Katsuhiro Shimohigashi, Jun Etoh, Katsutaka Kimura
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Patent number: 5455797Abstract: An apparatus includes a constant voltage generator for generating a voltage based on a difference between threshold voltages of two MOS transistors, and a voltage sampling device for sampling the output voltage of the constant voltage generator circuit, wherein the voltage sampling device samples the output voltage of the constant voltage generator before an electric source switch for the constant voltage generator is turned off.Type: GrantFiled: October 4, 1994Date of Patent: October 3, 1995Assignees: Hitachi, Ltd., Hitachi VLSI Engineering CorporationInventors: Jun Etoh, Yoshinobu Nakagome, Hitoshi Tanaka, Koji Kawamoto, Masakazu Aoki
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Patent number: 5426616Abstract: A voltage conversion circuit of the present invention is equipped with means for generating a first voltage stabilized with respect to ground potential of a semiconductor integrated circuit device including the circuit, means for generating second voltage stabilized with respect to an external supply voltage of the semiconductor integrated circuit device, and selection means for selecting either the first voltage or the second voltage. The first voltage age, stabilized with respect to the ground potential, is selected and used as the voltage at the time of normal operation, and the second voltage, stabilized with respect to the external supply voltage, is selected and used at the time of aging test. In this case, means for trimming the first voltage and/or the second voltage is, preferably, provided to raise the voltage accuracy.Type: GrantFiled: May 16, 1994Date of Patent: June 20, 1995Assignee: Hitachi, Ltd.Inventors: Kazuhiko Kajigaya, Tetsu Udagawa, Kyoko Ishii, Manabu Tsunozaki, Kazuyoshi Oshima, Masashi Horiguchi, Jun Etoh, Masakazu Aoki, Shin'ichi Ikenaga, Kiyoo Itoh
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Patent number: 5402376Abstract: In a semiconductor memory, switch circuits are provided so as to inhibit voltage and signal supplies to each of the normal memory blocks when so required. On the other hand, a ROM is provided on the chip so as to store the address of a defective memory block which consumes an excessively large stand-by current when the semiconductor memory is in the stand-by mode. The switch circuits are controlled by the output of the ROM so as to inhibit the voltage and signal supply to the defective memory block. Then, a spare memory block which is substituted for the defective normal memory block receives the voltage and signal supply.Type: GrantFiled: August 10, 1993Date of Patent: March 28, 1995Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Masashi Horiguchi, Jun Etoh, Masakazu Aoki, Yoshinobu Nakagome, Hitoshi Tanaka, Kiyoo Itoh
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Patent number: 5384740Abstract: An apparatus includes a constant voltage generator for generating a voltage based on a difference between threshold voltages of two MOS transistors, and a voltage sampling device for sampling the output voltage of the constant voltage generator circuit, wherein the voltage sampling device samples the output voltage of the constant voltage generator before an electric source switch for the constant voltage generator is turned off.Type: GrantFiled: December 21, 1993Date of Patent: January 24, 1995Assignees: Hitachi, Ltd., Hitachi ULSI EngineeringInventors: Jun Etoh, Yoshinobu Nakagome, Hitoshi Tanaka, Koji Kawamoto, Masakazu Aoki
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Patent number: 5383080Abstract: A voltage limiter circuit is disposed in a semiconductor IC chip in order to reduce an operating voltage of an internal circuit of a scaled-down element. A small capacitance of a Vcc wiring by the disposition constitutes a resonance circuit together with an inductance of the Vcc wiring. Resonance at the resonance circuit causes large variation of a supply current and noise. An additional capacitance is connected between the Vcc wiring and a Vss wiring in order to suppress the variation and noise. The capacitance is formed by a PN junction and is connected in series to a damping resistance.Type: GrantFiled: July 24, 1992Date of Patent: January 17, 1995Assignees: Hitachi, Ltd., Hitachi VLSI Engineering CorporationInventors: Jun Etoh, Masakazu Aoki, Masashi Horiguchi, Shigeki Ueda, Hitoshi Tanaka, Kazuhiko Kajigaya, Tsugio Takahashi, Hiroshi Kawamoto
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Patent number: 5376839Abstract: Practical structures of an ultra large scale semiconductor integrated (ULSI) circuit especially a dynamic random access memory of 16M bits or more are involved. The ULSI circuit uses internal operating voltages and how to construct a reference voltage generating circuit and a voltage limiter circuit in the ULSI circuit is a matter of importance. The operation of the reference voltage generating circuit and voltage limiter circuit can be stabilized, characteristics of these circuits are improved, and layout of these circuits as applied to memory cell array, peripheral circuits and the like can be improved. Improved methods of testing these circuits are provided.Type: GrantFiled: August 9, 1993Date of Patent: December 27, 1994Assignees: Hitachi Ltd., VLSI Engineering CorporationInventors: Masashi Horiguchi, Masakazu Aoki, Kiyoo Itoh, Yoshinobu Nakagome, Norio Miyake, Takaaki Noda, Jun Etoh, Hitoshi Tanaka, Shin'ichi Ikenaga
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Patent number: 5331596Abstract: An address multiplexed dynamic random access memory (RAM) which has both a normal operation mode and a test mode capability is provided. The test mode is initiated in response to particular signal level combinations of both the row address strobe (RAS) and column address strobe (CAS) signals and the write enable (WE) signal. Since the signal level combinations employed in connection with implementing the test mode are unused in the normal operating mode of the dynamic RAM, additional external terminals are unneeded. This dynamic RAM employs multiplexing circuitry on both the input side as well as on the output side of the dynamic RAM, which multiplexing circuitry is controlled during normal operation by select signals from a decoder and during the test mode by a test signal which allows accessing of data at all of the common complementary data lines by the testing circuitry so as to determine whether there is consistency or inconsistency of the data being read out for testing.Type: GrantFiled: May 26, 1992Date of Patent: July 19, 1994Assignee: Hitachi, Ltd.Inventors: Kazuyuki Miyazawa, Katsuhiro Shimohigashi, Jun Etoh, Katsutaka Kimura
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Patent number: 5297097Abstract: Disclosed is a one-chip ULSI which can carry out fixed operations for a wide range of power supply voltages (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which provides a fixed internal voltage for a wide range of power supply voltages, an input/output buffer which can be adapted to several input/out interface levels, a dynamic or volatile RAM(s) which can operate at a power supply voltage of 2 V or less, etc. This one-chip ULSI can be applied to compact and portable electronic devices such as a lap-top type personal computer, an electronic pocket note book, a solid-state camera, etc.Type: GrantFiled: June 14, 1989Date of Patent: March 22, 1994Assignees: Hitachi Ltd., Hitachi VLSI EngineeringInventors: Jun Etoh, Kiyoo Itoh, Yoshiki Kawajiri, Yoshinobu Nakagome, Eiji Kume, Hitoshi Tanaka
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Patent number: 5265055Abstract: A redundancy technique is introduced for a semiconductor memory and, more particularly a redundancy technique for a dynamic random access memory (DRAM) having a storage capacity of 16 mega bits or more. In such a DRAM, the efficiency of the redundancy technique is reduced, since a memory array is divided into a large number of memory mats.Type: GrantFiled: December 27, 1991Date of Patent: November 23, 1993Assignee: Hitachi, Ltd.Inventors: Masashi Horiguchi, Jun Etoh, Masakazu Aoki, Kiyoo Itoh
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Patent number: 5262999Abstract: Disclosed is a one-chip ULSI which can carry out the fixed operation in a wide range of power supply voltage (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which serves to a fixed internal voltage for a wide range of power supply voltage, an input/output buffer which can be adapted to several input/output levels, a dynamid RAM(s) which can operate at a power supply voltage of 2 V or less, etc. This one-chip ULSI can be applied to compact and portable electronic devices such as a lap-top type personal computer, an electronic pocket note book, a solid-state camera, etc.Type: GrantFiled: March 24, 1992Date of Patent: November 16, 1993Assignees: Hitachi, Ltd., Hitachi VLSI Engineering CorporationInventors: Jun Etoh, Kiyoo Itoh, Yoshiki Kawajiri, Yoshinobu Nakagome, Eiji Kume, Hitoshi Tanaka
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Patent number: 5262993Abstract: In a semiconductor memory, switch circuits are provided so as to inhibit voltage and signal supplies to each of the normal memory blocks when so required. On the other hand, a ROM is provided on the chip so as to store the address of a defective memory block which consumes an excessively large stand-by current when the semiconductor memory is in the stand-by mode. The switch circuits are controlled by the output of the ROM so as to inhibit the voltage and signal supply to the defective memory block. Then, a spare memory block which is substituted for the defective normal memory block receives the voltage and signal supply.Type: GrantFiled: November 6, 1991Date of Patent: November 16, 1993Assignees: Hitachi, Ltd., Hitachi VLSI Engineering CorporationInventors: Masashi Horiguchi, Jun Etoh, Masakazu Aoki, Yoshinobu Nakagome, Hitoshi Tanaka, Kiyoo Itoh
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Patent number: 5254880Abstract: Practical structures of an ultra large scale semiconductor integrated (ULSI) circuit especially a dynamic random access memory of 16M bits or more are involved. The ULSI circuit uses internal operating voltages and how to construct a reference voltage generating circuit and a voltage limiter circuit in the ULSI circuit is a matter of importance. The operation of the reference voltage generating circuit and voltage limiter circuit can be stabilized, characteristics of these circuits are improved, and layout of these circuits as applied to memory cell array, peripheral circuits and the like can be improved. Improved methods of testing these circuits are provided.Type: GrantFiled: April 3, 1992Date of Patent: October 19, 1993Assignees: Hitachi, Ltd., Hitachi VLSI Engineering CorporationInventors: Masashi Horiguchi, Masakazu Aoki, Kiyoo Itoh, Yoshinobu Nakagome, Norio Miyake, Takaaki Noda, Jun Etoh, Hitoshi Tanaka, Shin ichi Ikenaga
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Patent number: 5179539Abstract: Practical structures of an ultra large scale semiconductor integrated (ULSI) circuit especially a dynamic random access memory of 16 M bits or more are involved. The ULSI circuit uses internal operating voltages and how to construct a reference voltage generating circuit and a voltage limiter circuit in the ULSI circuit is a matter of importance. The operation of the reference voltage generating circuit and voltage limiter circuit can be stabilized, characteristics of these circuits are improved, and layout of these circuits as applied to memory cell array, peripheral circuits and the like can be improved. Improved methods of testing these circuits are provided.Type: GrantFiled: April 8, 1992Date of Patent: January 12, 1993Assignee: Hitachi, Ltd., Hitachi Vlsi Engineering CorporationInventors: Masashi Horiguchi, Masakazu Aoki, Kiyoo Itoh, Yoshinobu Nakagome, Norio Miyake, Takaaki Noda, Jun Etoh, Hitoshi Tanaka, Shin'ichi Ikenaga
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Patent number: 5117393Abstract: An address multiplexed dynamic RAM device is provided which is capable of initiating (setting) and terminating (resetting) the test mode in response to the signal level combinations of the row address and column address strobe signals and the write enable signal. The signal level combinations employed correspond to those which are unused in the normal operating mode thereby obviating the need for providing additional external control signal terminals. In addition to writing predetermined data in selected memory cells during the test mode, verficiation of the predetermined data is also implemented during the read phase of the test mode.Type: GrantFiled: January 31, 1991Date of Patent: May 26, 1992Assignee: Hitachi, Ltd.Inventors: Kazuyuki Miyazawa, Katsuhiro Shimohigashi, Jun Etoh, Katsutaka Kimura
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Patent number: 5086414Abstract: A semiconductor circuit having a plurality of circuit blocks, each having latch circuits each one thereof being controlled by an internally provided clock signal for preventing malfunction of the circuit. Each circuit is provided with the latch function so that the cycle time is made shorter than the access time. Moreover, the latch means are driven in such a manner that the adjoining ones are prevented from being put to through-state simultaneously, whereby malfunction is prevented.Type: GrantFiled: November 15, 1989Date of Patent: February 4, 1992Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Hiroaki Nambu, Noriyuki Homma, Kunihiko Yamaguchi, Kazuo Kanetani, Youji Idei, Kenichi Ohhata, Yoshiaki Sakurai, Jun Etoh
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Patent number: 4994688Abstract: Practical structures of an ultra large scale semiconductor integrated (ULSI) circuit especially a dynamic random access memory of 16 M bits or more are involved. The ULSI circuit uses internal operating voltages and how to construct a reference voltage generating circuit and a voltage limiter circuit in the ULSI circuit is a matter of importance. The operation of the reference voltage generating circuit and voltage limiter circuit can be stabilized, characteristics of these circuits are improved, and layout of these circuits as applied to memory cell array, peripheral circuits and the like can be improved. Improved methods of testing these circuits are provided.Type: GrantFiled: March 15, 1989Date of Patent: February 19, 1991Assignees: Hitachi Ltd., Hitachi VLSI Engineering CorporationInventors: Masashi Horiguchi, Masakazu Aoki, Kiyoo Itoh, Yoshinobu Nakagome, Norio Miyake, Takaaki Noda, Jun Etoh, Hitoshi Tanaka, Shin'ichi Ikenaga