Patents by Inventor Jun-hee Cho

Jun-hee Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190065034
    Abstract: A device and a method of setting an input detection region of a user interface displayed on a display of an electronic device are provided. The electronic device displays user interfaces in a first region, receives user input through the display from the outside of the first region, checks whether the user input was provided by a finger or electronic pen, determines whether the user input is in a second region, which is adjacent to the first region and surrounds the first region, when the user input was provided by a finger, determines whether the user input is in a third region, which is adjacent to the first region, surrounds the first region, and is positioned inside the second region, when the user input was provided by an electronic pen, and enables the application to use the user input, as if the user input was provided in the first region.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 28, 2019
    Inventors: Seong-Hoon CHOI, Jaesook JOO, Yong-Jin KWON, Hyoung-Youn NA, Jeongsik MUN, Gyehun JEON, Bohwa CHUNG, Jun-Hee CHO, Seung HEO
  • Patent number: 8779493
    Abstract: A semiconductor device includes a trench formed in a predetermined portion of a substrate and a first recess region beneath the trench. A field oxide layer is buried into both the trench and the first recess region. An active region is defined by the field oxide layer, having first active region and a second active region. The latter has a second recess region formed in lower portion of the active region than the former. A step gate pattern is formed on border region between the first active region and the second active region. The gate pattern has step structure whose one side extends to a surface of the first active region and the other side extends to a surface of the second active region. Other embodiments are also described.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: July 15, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jun-Hee Cho
  • Patent number: 8236696
    Abstract: A method for fabricating a semiconductor device to enlarge a channel region is provided. The channel region is enlarged due to having pillar shaped sidewalls of a transistor. The transistor includes a fin active region vertically protruding on a substrate, an isolation layer enclosing a lower portion of the fin active region, and a gate electrode crossing the fin active region and covering a portion of the fin active region. An isolation layer is formed enclosing a lower portion of the fin active region and the isolation layer under the spacers is partially removed to expose a portion of the sidewalls of the fin active region. Subsequently, dry etching is performed to form the sidewalls having a pillar/neck.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: August 7, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jun-Hee Cho
  • Publication number: 20120080743
    Abstract: A semiconductor device includes a trench formed in a predetermined portion of a substrate and a first recess region beneath the trench. A field oxide layer is buried into both the trench and the first recess region. An active region is defined by the field oxide layer, having first active region and a second active region. The latter has a second recess region formed in lower portion of the active region than the former. A step gate pattern is formed on border region between the first active region and the second active region. The gate pattern has step structure whose one side extends to a surface of the first active region and the other side extends to a surface of the second active region. Other embodiments are also described.
    Type: Application
    Filed: October 4, 2011
    Publication date: April 5, 2012
    Inventor: Jun-Hee Cho
  • Patent number: 8049262
    Abstract: A semiconductor device includes a trench formed in a predetermined portion of a substrate and a first recess region beneath the trench. A field oxide layer is buried into both the trench and the first recess region. An active region is defined by the field oxide layer, having a first active region and a second active region. The latter has a second recess region formed in a lower portion of the active region than the former. A step gate pattern is formed on a border region between the first active region and the second active region. The gate pattern has a step structure whose one side extends to a surface of the first active region and the other side extends to a surface of the second active region. Other embodiments are also described.
    Type: Grant
    Filed: August 13, 2007
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Jun-Hee Cho
  • Patent number: 7977196
    Abstract: A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of the active region.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: July 12, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jun-Hee Cho
  • Patent number: 7977749
    Abstract: A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of the active region.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: July 12, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jun-Hee Cho
  • Publication number: 20110003450
    Abstract: A method for forming a semiconductor device includes forming a gate pattern over a silicon substrate, forming gate spacers over both sidewalls of the gate pattern, forming a dummy gate spacer over a sidewall of each one of the gate spacers, forming a recess region having inclined sidewalls extending in a direction to a channel region under the gate pattern by recess-etching the silicon substrate, filling the recess region with an epitaxial film, which becomes a source region or a drain region, through a selective epitaxial growth process, and removing the dummy gate spacer.
    Type: Application
    Filed: December 23, 2009
    Publication date: January 6, 2011
    Inventors: Young-Ho LEE, Tae-Hang Ahn, Seung-Beom Baek, Jun-Hee Cho, Jeong-Seon Kim
  • Patent number: 7749843
    Abstract: A method for fabricating a semiconductor device with a bulb-shaped recess gate pattern is provided. The method includes forming a plurality of oxide layers over a substrate; forming a silicon layer to cover the oxide layers; forming a mask over the silicon layer; etching the silicon layer using the mask as an etch mask to form a plurality of first recesses to expose the oxide layers; etching the oxide layers to form a plurality of second recesses; and forming a plurality of gate patterns at least partially buried into the first recesses and the second recesses.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: July 6, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Jun-Hee Cho
  • Publication number: 20100105183
    Abstract: A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of the active region.
    Type: Application
    Filed: December 28, 2009
    Publication date: April 29, 2010
    Applicant: Hynix Semiconductor Inc.
    Inventor: Jun-Hee CHO
  • Publication number: 20100096690
    Abstract: A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of the active region.
    Type: Application
    Filed: December 28, 2009
    Publication date: April 22, 2010
    Applicant: Hynix Semiconductor Inc.
    Inventor: Jun-Hee CHO
  • Patent number: 7682885
    Abstract: A method for fabricating a semiconductor device includes forming a sacrificial layer over a substrate, forming a contact hole in the sacrificial layer, forming a pillar to fill the contact hole. The pillar laterally extends up to a surface of the sacrificial layer and then the sacrificial layer is removed. The method further includes forming a gate dielectric layer over an exposed sidewall of the pillar, and forming a gate electrode over the gate dielectric layer. The gate electrode surrounds the sidewall of the pillar.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: March 23, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jun-Hee Cho, Sang-Hoon Park
  • Patent number: 7651907
    Abstract: A method for fabricating a semiconductor device, the method includes forming an etch stop layer and an insulation layer over a substrate having a first region and a second region, selectively removing the insulation layer and the etch stop layer in the first region to expose parts of the substrate, thereby forming at least two electrode regions on the exposed substrate and a resultant structure, forming a conductive layer over the resultant structure, removing the conductive layer in the second region, removing the insulation layer in the first region and the second region by using wet chemicals, and removing parts of the conductive layer, which formed between the at least two electrode regions in the first region, to form cylinder type electrodes in the first region.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: January 26, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jun-Hee Cho
  • Patent number: 7638398
    Abstract: A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of the active region.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: December 29, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jun-Hee Cho
  • Patent number: 7585727
    Abstract: A method for fabricating a semiconductor device includes etching a portion of a substrate to form a recess. A polymer layer fills a lower portion of the recess. Sidewall spacers are formed over the recess above the lower portion of the recess. The polymer layer is removed. The lower portion of the recess is isotropically etching to form a bulb-shaped recess.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: September 8, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jun-Hee Cho
  • Publication number: 20090163000
    Abstract: A method for fabricating a semiconductor device includes forming a sacrificial layer over a substrate, forming a contact hole in the sacrificial layer, forming a pillar to fill the contact hole. The pillar laterally extends up to a surface of the sacrificial layer and then the sacrificial layer is removed. The method further includes forming a gate dielectric layer over an exposed sidewall of the pillar, and forming a gate electrode over the gate dielectric layer. The gate electrode surrounds the sidewall of the pillar.
    Type: Application
    Filed: June 30, 2008
    Publication date: June 25, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Jun-Hee CHO, Sang-Hoon PARK
  • Publication number: 20080305608
    Abstract: A method for fabricating a semiconductor device, the method includes forming an etch stop layer and an insulation layer over a substrate having a first region and a second region, selectively removing the insulation layer and the etch stop layer in the first region to expose parts of the substrate, thereby forming at least two electrode regions on the exposed substrate and a resultant structure, forming a conductive layer over the resultant structure, removing the conductive layer in the second region, removing the insulation layer in the first region and the second region by using wet chemicals, and removing parts of the conductive layer, which formed between the at least two electrode regions in the first region, to form cylinder type electrodes in the first region.
    Type: Application
    Filed: December 26, 2007
    Publication date: December 11, 2008
    Inventor: Jun-Hee Cho
  • Publication number: 20080230832
    Abstract: A method for fabricating a semiconductor device to enlarge a channel region is provided. The channel region is enlarged due to having pillar shaped sidewalls of a transistor. The transistor includes a fin active region vertically protruding on a substrate, an isolation layer enclosing a lower portion of the fin active region, and a gate electrode crossing the fin active region and covering a portion of the fin active region. An isolation layer is formed enclosing a lower portion of the fin active region and the isolation layer under the spacers is partially removed to expose a portion of the sidewalls of the fin active region. Subsequently, dry etching is performed to form the sidewalls having a pillar/neck.
    Type: Application
    Filed: December 27, 2007
    Publication date: September 25, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventor: Jun-Hee CHO
  • Publication number: 20080087980
    Abstract: A semiconductor structure has an active region on a substrate, and recessed portions are formed at lower edges of lateral portions of the semiconductor structure. Patterned first insulation layers for device isolation are buried into the recessed portions. Second insulation layers for device isolation are formed on sidewalls of the first insulation layers.
    Type: Application
    Filed: December 4, 2007
    Publication date: April 17, 2008
    Inventor: Jun-Hee Cho
  • Patent number: 7354828
    Abstract: A semiconductor device includes a trench formed in a predetermined portion of a substrate and a first recess region beneath the trench. A field oxide layer is buried into both the trench and the first recess region. An active region is defined by the field oxide layer, having a first active region and a second active region. The latter has a second recess region formed in a lower portion of the active region than the former. A step gate pattern is formed on a border region between the first active region and the second active region. The gate pattern has a step structure whose one side extends to a surface of the first active region and the other side extends to a surface of the second active region. Other embodiments are also described.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: April 8, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jun-Hee Cho