Patents by Inventor Jun-hee Cho

Jun-hee Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190386117
    Abstract: A method for manufacturing a semiconductor device includes forming a gate insulation film and a polysilicon layer on a substrate, forming a polysilicon pattern by etching the polysilicon layer, forming an opening in the polysilicon pattern that exposes a part of the polysilicon pattern by forming a mask pattern on the polysilicon pattern, forming a gate electrode by etching the part of the polysilicon pattern exposed through the opening, forming a P-type body region by ion implanting a P-type dopant onto the substrate using the gate electrode as a mask, forming an N-type LDD region on the P-type body region by ion implanting an N-type dopant onto the substrate using the gate electrode as a mask, forming a spacer on a side surface of the gate electrode, and forming an N-type source region on a side surface of the spacer.
    Type: Application
    Filed: October 17, 2018
    Publication date: December 19, 2019
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Tae Hoon LEE, Jun Hee CHO, Jin Seong CHUNG
  • Publication number: 20190288066
    Abstract: A power semiconductor device includes a drain region and a source region disposed on a substrate, a gate insulating layer and a gate electrode disposed on the substrate and disposed between the drain region and the source region, a protection layer in contact with a top surface of the substrate and a top surface of the gate electrode, a source contact plug connected to the source region, a drain contact plug connected to the drain region, and a field plate plug in contact with the protection layer, wherein a width of the field plate plug is greater than a width of the source contact plug or a width of the drain contact plug.
    Type: Application
    Filed: August 3, 2018
    Publication date: September 19, 2019
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Tae Hoon LEE, Jun Hee CHO, Jin Seong CHUNG
  • Publication number: 20190065034
    Abstract: A device and a method of setting an input detection region of a user interface displayed on a display of an electronic device are provided. The electronic device displays user interfaces in a first region, receives user input through the display from the outside of the first region, checks whether the user input was provided by a finger or electronic pen, determines whether the user input is in a second region, which is adjacent to the first region and surrounds the first region, when the user input was provided by a finger, determines whether the user input is in a third region, which is adjacent to the first region, surrounds the first region, and is positioned inside the second region, when the user input was provided by an electronic pen, and enables the application to use the user input, as if the user input was provided in the first region.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 28, 2019
    Inventors: Seong-Hoon CHOI, Jaesook JOO, Yong-Jin KWON, Hyoung-Youn NA, Jeongsik MUN, Gyehun JEON, Bohwa CHUNG, Jun-Hee CHO, Seung HEO
  • Publication number: 20180316178
    Abstract: Provided is a black box apparatus for analyzing a cause of arc interruption including: a controller which is installed on a power supply line and receives data detected from a CT detecting a current, a ZCT detecting a short circuit, and a voltage detector detecting a voltage; and an interruption unit which interrupts a power supply by receive a signal from the controller to operate a switch, in which the controller includes a calculation unit calculating data detected from the CT, the ZCT, and the voltage detector; a determination unit determining whether the arc occurs using the result of the calculation unit; and a storage unit storing data up to a predetermined time before the operation when the interruption unit operates to interrupt the power supply. Therefore, it is possible to accurately analyze reproduction for preventing occurrence of electrical fires and a cause of the arc interruption and determine an unstable condition of a power supply device which instantaneously occurs.
    Type: Application
    Filed: April 26, 2018
    Publication date: November 1, 2018
    Inventors: Jun Bae LEE, Kyeong Min HONG, Jun Hee CHO
  • Publication number: 20180246634
    Abstract: An electronic device includes a touch screen display, an input/output interface, a communication circuit, a memory, and a processor, and the processor modifies screen configuration information associated with at least a part of a resolution, a density, and an orientation of a screen output by the electronic device if the electronic device is connected to the external display device through the input/output interface, determines whether a target application to be displayed on the external display device supports resizing of a window that displays an execution screen of the target application, configures a first type of window which is resizable if the target application supports the resizing, configures a second type of window with a fixed size if the target application does not support the resizing, and displays the first type of window or the second type of window on the external display device.
    Type: Application
    Filed: February 28, 2018
    Publication date: August 30, 2018
    Inventors: Jae Woo SUH, Young Kyu SEON, Seong Hoon CHOI, Jong Seung BAEK, Jeong Won YANG, Kwang Ho LIM, So Jung JANG, Gye Hun JEON, Byung Seok JUNG, Jun Hee CHO, Jae Sook JOO, Seung HEO, Ga Jin SONG
  • Publication number: 20180062372
    Abstract: An arc detection apparatus is provided. The arc detection apparatus detects an arc using an electrical energy, eliminates the possibility of a false arc detection caused by noise due to a power environment, increases accuracy of arc detection, and prevents fires that may occur in a home or an industrial site due to an arc occurrence.
    Type: Application
    Filed: July 31, 2017
    Publication date: March 1, 2018
    Applicant: KEPID AMSTECH CO., LTD.
    Inventors: Jun Bae LEE, Kyeong Min HONG, Jun Hee CHO
  • Patent number: 8797434
    Abstract: Disclosed are a CMOS image sensor having a wide dynamic range and a sensing method thereof. Each unit pixel of the CMOS image sensor of the present invention includes multiple processing units, so that one shuttering section for the image generation of one image frame can be divided into multiple sections to separately shutter and sample the divided sections by each processing unit. Thus, the image sensor of the present invention enables many shuttering actions to be performed in the multiple processing units, respectively, and the multiple processing units to separately sample each floating diffusion voltage caused by the shuttering actions, thereby realizing a wide dynamic range.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: August 5, 2014
    Assignee: Zeeann Co., Ltd
    Inventors: Jawoong Lee, Jun hee Cho, Jong Beom Choi
  • Patent number: 8779493
    Abstract: A semiconductor device includes a trench formed in a predetermined portion of a substrate and a first recess region beneath the trench. A field oxide layer is buried into both the trench and the first recess region. An active region is defined by the field oxide layer, having first active region and a second active region. The latter has a second recess region formed in lower portion of the active region than the former. A step gate pattern is formed on border region between the first active region and the second active region. The gate pattern has step structure whose one side extends to a surface of the first active region and the other side extends to a surface of the second active region. Other embodiments are also described.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: July 15, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jun-Hee Cho
  • Patent number: 8236696
    Abstract: A method for fabricating a semiconductor device to enlarge a channel region is provided. The channel region is enlarged due to having pillar shaped sidewalls of a transistor. The transistor includes a fin active region vertically protruding on a substrate, an isolation layer enclosing a lower portion of the fin active region, and a gate electrode crossing the fin active region and covering a portion of the fin active region. An isolation layer is formed enclosing a lower portion of the fin active region and the isolation layer under the spacers is partially removed to expose a portion of the sidewalls of the fin active region. Subsequently, dry etching is performed to form the sidewalls having a pillar/neck.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: August 7, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jun-Hee Cho
  • Publication number: 20120080743
    Abstract: A semiconductor device includes a trench formed in a predetermined portion of a substrate and a first recess region beneath the trench. A field oxide layer is buried into both the trench and the first recess region. An active region is defined by the field oxide layer, having first active region and a second active region. The latter has a second recess region formed in lower portion of the active region than the former. A step gate pattern is formed on border region between the first active region and the second active region. The gate pattern has step structure whose one side extends to a surface of the first active region and the other side extends to a surface of the second active region. Other embodiments are also described.
    Type: Application
    Filed: October 4, 2011
    Publication date: April 5, 2012
    Inventor: Jun-Hee Cho
  • Publication number: 20120033118
    Abstract: Disclosed are a CMOS image sensor having a wide dynamic range and a sensing method thereof. Each unit pixel of the CMOS image sensor of the present invention includes multiple processing units, so that one shuttering section for the image generation of one image frame can be divided into multiple sections to separately shutter and sample the divided sections by each processing unit. Thus, the image sensor of the present invention enables many shuttering actions to be performed in the multiple processing units, respectively, and the multiple processing units to separately sample each floating diffusion voltage caused by the shuttering actions, thereby realizing a wide dynamic range.
    Type: Application
    Filed: March 10, 2010
    Publication date: February 9, 2012
    Applicant: ZEEANN CO., LTD.
    Inventors: Jawoong Lee, Jun hee Cho, Jong Beom Choi
  • Patent number: 8049262
    Abstract: A semiconductor device includes a trench formed in a predetermined portion of a substrate and a first recess region beneath the trench. A field oxide layer is buried into both the trench and the first recess region. An active region is defined by the field oxide layer, having a first active region and a second active region. The latter has a second recess region formed in a lower portion of the active region than the former. A step gate pattern is formed on a border region between the first active region and the second active region. The gate pattern has a step structure whose one side extends to a surface of the first active region and the other side extends to a surface of the second active region. Other embodiments are also described.
    Type: Grant
    Filed: August 13, 2007
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Jun-Hee Cho
  • Patent number: 7977749
    Abstract: A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of the active region.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: July 12, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jun-Hee Cho
  • Patent number: 7977196
    Abstract: A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of the active region.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: July 12, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jun-Hee Cho
  • Publication number: 20110003450
    Abstract: A method for forming a semiconductor device includes forming a gate pattern over a silicon substrate, forming gate spacers over both sidewalls of the gate pattern, forming a dummy gate spacer over a sidewall of each one of the gate spacers, forming a recess region having inclined sidewalls extending in a direction to a channel region under the gate pattern by recess-etching the silicon substrate, filling the recess region with an epitaxial film, which becomes a source region or a drain region, through a selective epitaxial growth process, and removing the dummy gate spacer.
    Type: Application
    Filed: December 23, 2009
    Publication date: January 6, 2011
    Inventors: Young-Ho LEE, Tae-Hang Ahn, Seung-Beom Baek, Jun-Hee Cho, Jeong-Seon Kim
  • Patent number: 7749843
    Abstract: A method for fabricating a semiconductor device with a bulb-shaped recess gate pattern is provided. The method includes forming a plurality of oxide layers over a substrate; forming a silicon layer to cover the oxide layers; forming a mask over the silicon layer; etching the silicon layer using the mask as an etch mask to form a plurality of first recesses to expose the oxide layers; etching the oxide layers to form a plurality of second recesses; and forming a plurality of gate patterns at least partially buried into the first recesses and the second recesses.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: July 6, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Jun-Hee Cho
  • Publication number: 20100105183
    Abstract: A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of the active region.
    Type: Application
    Filed: December 28, 2009
    Publication date: April 29, 2010
    Applicant: Hynix Semiconductor Inc.
    Inventor: Jun-Hee CHO
  • Publication number: 20100096690
    Abstract: A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of the active region.
    Type: Application
    Filed: December 28, 2009
    Publication date: April 22, 2010
    Applicant: Hynix Semiconductor Inc.
    Inventor: Jun-Hee CHO
  • Patent number: 7682885
    Abstract: A method for fabricating a semiconductor device includes forming a sacrificial layer over a substrate, forming a contact hole in the sacrificial layer, forming a pillar to fill the contact hole. The pillar laterally extends up to a surface of the sacrificial layer and then the sacrificial layer is removed. The method further includes forming a gate dielectric layer over an exposed sidewall of the pillar, and forming a gate electrode over the gate dielectric layer. The gate electrode surrounds the sidewall of the pillar.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: March 23, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jun-Hee Cho, Sang-Hoon Park
  • Patent number: 7651907
    Abstract: A method for fabricating a semiconductor device, the method includes forming an etch stop layer and an insulation layer over a substrate having a first region and a second region, selectively removing the insulation layer and the etch stop layer in the first region to expose parts of the substrate, thereby forming at least two electrode regions on the exposed substrate and a resultant structure, forming a conductive layer over the resultant structure, removing the conductive layer in the second region, removing the insulation layer in the first region and the second region by using wet chemicals, and removing parts of the conductive layer, which formed between the at least two electrode regions in the first region, to form cylinder type electrodes in the first region.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: January 26, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jun-Hee Cho