Patents by Inventor Jun Ho Seo
Jun Ho Seo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210225451Abstract: A program method of a nonvolatile memory device including receiving a write address and write data, generating a seed corresponding to the write address, generating a random sequence by using the seed, randomizing the write data by using the random sequence, and programming the randomized write data to a memory area corresponding to the write address may be provided. The seed may provide state shaping variable depending on a location of a word line, at which the received write data is to be programmed.Type: ApplicationFiled: November 16, 2020Publication date: July 22, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Jun-ho SEO, Sangwon HWANG, Suk-Eun KANG, Haneol JANG, Youngwook JEONG, Wanha HWANG
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Patent number: 11017838Abstract: A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.Type: GrantFiled: August 12, 2020Date of Patent: May 25, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hee-Woong Kang, Dong-Hun Kwak, Jun-Ho Seo, Hee-Won Lee
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Publication number: 20210136688Abstract: An application processor and a system on chip (SoC) that incorporates the application processor are provided. The application processor includes a first core configured to process first data per unit time, a second core configured to process second data larger than the first data per unit time, and a lookup table configured to determine whether to activate the first core or the second core based on at least one of an analysis result of a message signal received by a communications processor, a sensing signal supplied to the application processor and a power level supplied to the communications processor.Type: ApplicationFiled: January 14, 2021Publication date: May 6, 2021Inventors: TAEK KYUN SHIN, JUN HO SEO, JUNG HUN HEO
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Patent number: 10934370Abstract: The invention relates to: a hybrid supported metallocene catalyst includes at least one first metallocene compound among the compounds represented by chemical formula 1, at least one second metallocene compound among the compounds represented by chemical formula 2 and a cocatalyst compound; a method for preparing an ethylene-?-olefin copolymer, comprising polymerizing olefin monomers in the presence thereof; and an ethylene-?-olefin copolymer having improved melt strength.Type: GrantFiled: March 29, 2016Date of Patent: March 2, 2021Assignee: HANWHA CHEMICAL CORPORATIONInventors: Ah Ra Cho, Ah Reum Kim, Lan Hua Piao, Jun Ho Seo, Song Hee Yang, So Jung Lee, Yu Jeong Lim, Dong Wook Jeong, Seung Il Choi
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Patent number: 10897738Abstract: An application processor and a system on chip (SoC) that incorporates the application processor are provided. The application processor includes a first core configured to process first data per unit time, a second core configured to process second data larger than the first data per unit time, and a lookup table configured to determine whether to activate the first core or the second core based on at least one of an analysis result of a message signal received by a communications processor, a sensing signal supplied to the application processor and a power level supplied to the communications processor.Type: GrantFiled: December 27, 2016Date of Patent: January 19, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Taek Kyun Shin, Jun Ho Seo, Jung Hun Heo
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Publication number: 20200372945Abstract: A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.Type: ApplicationFiled: August 12, 2020Publication date: November 26, 2020Inventors: Hee-Woong KANG, Dong-Hun KWAK, Jun-Ho SEO, Hee-Won LEE
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Patent number: 10785860Abstract: A dual frequency power-driven inductively coupled plasma torch according to an exemplary embodiment of the present invention includes: a hollow confinement tube provided with a space in which thermal plasma is formed; an induction coil that surrounds the confinement tube; and a power supply source that supplies power to the induction coil, wherein the power supply source may supply at least two powers having different frequencies to the induction coil.Type: GrantFiled: June 23, 2016Date of Patent: September 22, 2020Assignees: KOREA INSTITUTE OF MACHINERY & MATERIALS, INDUSTRIAL COOPERATION FOUNDATION OF CHONBUK NATIONAL UNIVERSITYInventors: Hee-Chang Park, Dong-Won Yun, Jun-Ho Seo, Junseok Nam, Mi-Yeon Lee, Jeong-Soo Kim
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Patent number: 10777254Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.Type: GrantFiled: March 13, 2020Date of Patent: September 15, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Hun Kwak, Hee-Woong Kang, Jun-Ho Seo, Hee-Won Lee
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Publication number: 20200219552Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.Type: ApplicationFiled: March 13, 2020Publication date: July 9, 2020Inventors: Dong-Hun KWAK, Hee-Woong KANG, Jun-Ho SEO, Hee-Won LEE
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Publication number: 20200171626Abstract: A substrate treatment apparatus is provided. The substrate treatment apparatus includes a substrate support part provided with a seating surface and configured to support a substrate, a guide ring annularly disposed along an edge of the substrate support part to surround the substrate, and a centering part provided inside the guide ring and configured to center the substrate by moving in a direction parallel to the seating surface to pressurize the edge of the substrate.Type: ApplicationFiled: November 25, 2019Publication date: June 4, 2020Inventors: Ki Sang Eum, Byoung Ok Kim, Jae Hun Jeong, Ju Eun Kim, Jun Ho Seo, Man Kyu Kang
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Patent number: 10672454Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.Type: GrantFiled: November 6, 2019Date of Patent: June 2, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Hun Kwak, Hee-Woong Kang, Jun-Ho Seo, Hee-Won Lee
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Patent number: 10629254Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.Type: GrantFiled: November 7, 2018Date of Patent: April 21, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Hun Kwak, Hee-Woong Kang, Jun-Ho Seo, Hee-Won Lee
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Publication number: 20200075078Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.Type: ApplicationFiled: November 6, 2019Publication date: March 5, 2020Inventors: Dong-Hun KWAK, Hee-Woong KANG, Jun-Ho SEO, Hee-Won LEE
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Patent number: 10372626Abstract: A system-on-chip includes a magnetic random access memory and a security interface. The magnetic random access memory includes a plurality of memory areas, each of the plurality of memory areas having a different security level. The security interface circuitry configured to: identify a memory area from among the plurality of memory areas based on a received memory address associated with a received memory command; determine a security level associated with the identified memory area; and perform a memory operation on received data based on the received memory command and the determined security level.Type: GrantFiled: January 26, 2017Date of Patent: August 6, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Won Jung, Sungkyoung Kim, Jun-Ho Seo, Taekkyun Shin, Sang-hwa Jin
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Publication number: 20190074048Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.Type: ApplicationFiled: November 7, 2018Publication date: March 7, 2019Inventors: Dong-Hun KWAK, Hee-Woong KANG, Jun-Ho SEO, Hee-Won LEE
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Publication number: 20190023816Abstract: The invention relates to: a hybrid supported metallocene catalyst includes at least one first metallocene compound among the compounds represented by chemical formula 1, at least one second metallocene compound among the compounds represented by chemical formula 2 and a cocatalyst compound; a method for preparing an ethylene-?-olefin copolymer, comprising polymerizing olefin monomers in the presence thereof; and an ethylene-?-olefin copolymer having improved melt strength.Type: ApplicationFiled: March 29, 2016Publication date: January 24, 2019Applicant: HANWHA CHEMICAL CORPORATIONInventors: Ah Ra Cho, Ah Reum Kim, Lan Hua Piao, Jun Ho Seo, Song Hee Yang, So Jung Lee, Yu Jeong Lim, Dong Wook Jeong, Seung Il Choi
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Patent number: 10153029Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.Type: GrantFiled: May 24, 2017Date of Patent: December 11, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Hun Kwak, Hee-Woong Kang, Jun-Ho Seo, Hee-Won Lee
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Publication number: 20180192504Abstract: A dual frequency power-driven inductively coupled plasma torch according to an exemplary embodiment of the present invention includes: a hollow confinement tube provided with a space in which thermal plasma is formed; an induction coil that surrounds the confinement tube; and a power supply source that supplies power to the induction coil, wherein the power supply source may supply at least two powers having different frequencies to the induction coil.Type: ApplicationFiled: June 23, 2016Publication date: July 5, 2018Applicants: Korea Institute of Machinery & Materials, Industrial Cooperation Foundation of Chonbuk National UniversityInventors: Hee-Chang PARK, Dong-Won YUN, Jun-Ho SEO, Junseok NAM, Mi-Yeon LEE, Jeong-Soo KIM
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Publication number: 20180040362Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.Type: ApplicationFiled: May 24, 2017Publication date: February 8, 2018Inventors: Dong-Hun KWAK, Hee-Woong KANG, Jun-Ho SEO, Hee-Won LEE
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Publication number: 20170265137Abstract: An application processor and a system on chip (SoC) that incorporates the application processor are provided. The application processor includes a first core configured to process first data per unit time, a second core configured to process second data larger than the first data per unit time, and a lookup table configured to determine whether to activate the first core or the second core based on at least one of an analysis result of a message signal received by a communications processor, a sensing signal supplied to the application processor and a power level supplied to the communications processor.Type: ApplicationFiled: December 27, 2016Publication date: September 14, 2017Inventors: TAEK KYUN SHIN, JUN HO SEO, JUNG HUN HEO