Abstract: A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes a lower wire, an interlayer insulating film formed on the lower wire and having a via hole exposing the upper surface of the lower wire, a diffusion barrier formed on the inner wall of the via hole, and an upper wire filling the via hole and directly contacting the lower wire, in which a dopant region containing a component of the diffusion barrier is formed in the lower wire in the extension direction of the via hole.

Abstract: A method of removing an insulation layer pattern covering metal wires includes providing an insulation layer pattern on a substrate, the insulation layer pattern having openings exposing the substrate, forming metal wires in the openings by depositing a barrier layer on inner surfaces of the openings, such that a lower portion of the barrier layer is thinner that an upper portion of the barrier layer, and depositing a metal layer to fill the openings, and performing an etching process with an etching vapor to remove the insulation layer pattern from the substrate to expose the metal wires.

Abstract: An interconnection having a dual-level and multi-level capping layer and a method of forming the same. The interconnection may include an interlayer dielectric layer with a groove formed therein, a metal layer formed within the groove, a metal compound layer on the metal layer, a first barrier layer on the interlayer dielectric layer, and a second barrier layer on both the metal compound layer and the first barrier layer.

Abstract: An apparatus and method for selecting, releasing, and changing a MultiCast and BroadCast Service (MCBCS) of a Mobile Station (MS) in a Broadband Wireless Access (BWA) system are provided. The method includes, upon receiving a request to select a specific channel, transmitting a channel selection request message for selecting the channel; determining whether a DSA request message including a Media Access Control (MAC) layer name tag for the channel is received from an Access Service Network-Gateway (ASN-GW), and, upon receiving the DSA request message, transmitting a DSA response message to the ASN-GW; and receiving a channel selection response message including information indicating a success or failure of the channel selection from an MCBCS server. Accordingly, there is an advantage in that an overall transmission delay is reduced for an MCBCS call process, and a processing capacity can be effectively utilized.

Abstract: A handoff method between a source network to which a terminal is connected in order of a Base Station (BS) and an Access Service Network (ASN), and a target network to which the terminal is connected in order of a Packet Data Service Node (PDSN), a Packet Control Function (PCF) and an Access Network (AN). The terminal sends a handoff request message with AN information of the target network to the ASN via the BS. The ASN forwards the handoff request message to the PCF via the PDSN using the AN information. Upon receipt of the handoff request message, the PCF sends a request for session information to the ASN via the PDSN. The PDSN sends a request for context information to the ASN. Upon receipt of the session information request and the context information request, the ASN transfers the context information to the PDSN and transfers the session information to the AN via the PDSN and the PCF.

Abstract: In a method of manufacturing a semiconductor device having air gaps, an organic sacrificial layer pattern is formed on a semiconductor substrate, wherein the organic sacrificial layer pattern includes openings. Metal structures are formed in the openings. The organic sacrificial layer pattern is removed by a plasma ashing treatment using a source gas including oxygen (O2) and carbon monoxide (CO). An insulating interlayer is formed to have air gaps between the metal structures. Resistance-capacitance (RC) delay and crosstalk between the metal structures may be efficiently suppressed.

Abstract: Methods of fabricating a microelectronic device having improved performance characteristics are disclosed which are characterized by using super critical fluid to perform a material removal step. In one illustrative embodiment, the method includes preparing a substrate, forming an HSQ layer covering at least a portion of the substrate, and thereafter removing at least portions of the HSQ layer using super critical fluid CO2.

Abstract: A metal (e.g., copper) interconnect and related method of fabrication are disclosed in which the metal interconnect is formed by electro-plating a seed layer formed on a recess in a substrate before a metal layer is electro-plated to fill the recess.

Abstract: Disclosed is an apparatus and method for assigning resource in a mobile communication system. In an IP-based next generation mobile communication system, vocoder voice data between a media gateway and a base station controller is not concentrated into a particular vocoder resource but uniformly assigned to all vocoder resources, thereby contributing to efficient assignment of resources in the media gateway.

Abstract: A method of manufacturing a semiconductor element, includes forming a lower metal wiring layer and an interlayer insulating film on a substrate, forming an opening through the interlayer insulating film, such that the opening is in communication with an upper surface of the lower metal wiring layer, cleaning the opening, forming a metal wiring line protecting film in the opening, such that the metal wiring line protecting film covers the lower metal wiring layer, washing the opening to remove the metal wiring line protecting film, such that a top surface of the lower metal wiring layer is exposed, and drying the substrate.

Abstract: A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes a lower wire, an interlayer insulating film formed on the lower wire and having a via hole exposing the upper surface of the lower wire, a diffusion barrier formed on the inner wall of the via hole, and an upper wire filling the via hole and directly contacting the lower wire, in which a dopant region containing a component of the diffusion barrier is formed in the lower wire in the extension direction of the via hole.

Abstract: An interconnection having a dual-level and multi-level capping layer and a method of forming the same. The interconnection may include an interlayer dielectric layer with a groove formed therein, a metal layer formed within the groove, a metal compound layer on the metal layer, a first barrier layer on the interlayer dielectric layer, and a second barrier layer on both the metal compound layer and the first barrier layer.

Abstract: A CAVLC decoding method and apparatus is provided. In the method for decoding a coded bitstream using a CAVLC length table and a CAVLC value table, CAVLC length tables are re-sorted in an order of a codeword length and the coded bitstream is decoded using the re-sorted length table. Therefore, since data on a bitstream is sequentially read as much as a length suggested by the re-sorted table of the present invention, a memory access time is reduced and calculation complexity for comparing the CAVLC codewords is reduced.

Abstract: An interconnection structure and a method of fabricating the same are provided. The interconnection structure includes an interlayer insulating layer having a structure comprising a via hole structure or a trench-shaped line structure. A conformal metal diffusion barrier layer is disposed inside the via hole structure or the trench-shaped line structure of the interlayer insulating layer. An insulating diffusion barrier spacer is disposed to cover the metal diffusion barrier layer on the sidewalls of the via hole structure or the trench-shaped line structure of the interlayer insulating layer. In addition, a copper interconnection is disposed to fill the inside of the via hole structure or the trench-shaped line structure of the interlayer insulating layer.

Abstract: Etching solutions are disclosed for etching low-k dielectric layers on substrates, said solutions including effective proportions of an oxidant for oxidizing a low-k dielectric layer and effective proportions of an oxide etchant for removing oxides. It is possible to easily remove a low-k dielectric layer using such etching solutions by a single-stage treatment process.

Abstract: In a method for filling a hole with a metal, an insulating layer, a first mask layer and a second mask layer are successively formed on a semiconductor substrate. The first and second mask layers are etched using a photoresist pattern to form first and second masks. The first mask layer pattern is selectively etched using an etchant, the first mask layer pattern having a higher etching selectivity than the second layer pattern with respect to the etchant, to form a third mask layer pattern having a broadened opening. The insulating layer is etched using the second mask to form a hole in the insulating layer. A metal layer is formed in the hole and the third opening. The metal layer is planarized to form a metal plug buried in the hole without recesses or voids.

Abstract: Methods of fabricating a microelectronic device having improved performance characteristics are disclosed which are characterized by using super critical fluid to perform a material removal step. In one illustrative embodiment, the method includes preparing a substrate, forming an HSQ layer covering at least a portion of the substrate, and thereafter removing at least portions of the HSQ layer using super critical fluid CO2.

Abstract: A method of forming a conductive pattern includes preparing a semiconductor substrate having a conductive pattern, forming an interlayer dielectric pattern having an opening exposing the conductive pattern on the semiconductor substrate, forming a metal layer on the interlayer dielectric pattern to fill the opening, wet etching the metal layer, and polishing the metal layer to form a metal pattern filling the opening. The wet etching is done such that a top surface of the interlayer dielectric pattern is not exposed.

Abstract: In a method for filling a hole with a metal, an insulating layer, a first mask layer and a second mask layer are successively formed on a semiconductor substrate. The first and second mask layers are etched using a photoresist pattern to form first and second masks. The first mask layer pattern is selectively etched using an etchant, the first mask layer pattern having a higher etching selectivity than the second layer pattern with respect to the etchant, to form a third mask layer pattern having a broadened opening. The insulating layer is etched using the second mask to form a hole in the insulating layer. A metal layer is formed in the hole and the third opening. The metal layer is planarized to form a metal plug buried in the hole without recesses or voids.

Abstract: A method of forming a conductive metal line over a semiconductor wafer including forming a diffusion barrier layer over a top surface of the semiconductor wafer, and forming a seed metal layer over the diffusion barrier layer. A conductive metal layer is formed over the seed metal layer, the conductive metal layer selectively exposing a portion of the seed metal layer on the peripheral region of the semiconductor wafer. A partial etching process is performed on the conductive metal layer to remove the portion of the seed metal layer.