Abstract: An absorbent article (1) of the present invention has, in at least one of a front portion and a rear portion thereof, an elasticized portion (G) that is stretchable and contractible in an article lateral direction (Y). The elasticized portion (G) has an outer sheet (22) to be disposed on a side that is away from the skin of a wearer, an inner sheet (23) to be disposed on a side that is closer to the skin of the wearer than the outer sheet (22) is, and a plurality of elastic members (24) that are arranged between the outer and inner sheets in a state in which the elastic members are stretched in the article lateral direction (Y). The outer sheet (22) and the inner sheet (23) are partially joined to each other at a joined region (26). The joined region (26) is sandwiched between non-joined regions (36) where the outer sheet (22) and the inner sheet (23) are not continuously joined to each other in an article longitudinal direction or the article lateral direction.

Abstract: A solid-state image sensing apparatus including a solid-state image sensing device and a signal processing circuit. The solid-state image sensing device includes: a vertical transfer unit, composed of transfer columns corresponding to columns of the light-to-electric conversion elements, operable to transfer, in a vertical direction, signal charges read out from the light-to-electric conversion elements; a horizontal transfer unit operable to receive the signal charges from the vertical transfer unit and transfer them in a horizontal direction. The signal processing circuit converts the signal charges from the horizontal transfer unit into pixel data, and rearranges it into a two-dimensional array. In the rearrangement, the signal processing circuit, per transfer of one piece of pixel data, cyclically selects a line memory out of three line memories, writes a piece of pixel data into the selected line memory, or reads a row of pixel data from the selected line memory.

Abstract: A charge transfer implemented by a transfer section for transferring charges stored in image sensor elements along one direction on a surface where the image sensor elements are disposed is halted for a predetermined length of time. The charges are transferred from the transfer section without reading the charges from the image sensor elements after the charge transfer is halted for the predetermined length of time. A position where a defect is generated in an image pickup sensor is identified based on signal levels of the transferred charges. A defective signal level of the image pickup sensor generated on a line including the defect-generating position and in parallel with the one direction is corrected. As a result of the foregoing process, a display failure is precisely corrected.

Abstract: The panel interface control device, which eliminates the necessity of newly producing video data for panel display and flexibly responds to a change in the type of display panel, includes a data conversion circuit and an RGB filter circuit that are both programmable and scale up or down a digital video signal for display horizontally and vertically to conform to the screen size of the display panel. An interface section outputs the output of the RGB filter circuit to the display panel as video data.

Abstract: A charge transfer implemented by a transfer section for transferring charges stored in image sensor elements along one direction on a surface where the image sensor elements are disposed is halted for a predetermined length of time. The charges are transferred from the transfer section without reading the charges from the image sensor elements after the charge transfer is halted for the predetermined length of time. A position where a defect is generated in an image pickup sensor is identified based on signal levels of the transferred charges. A defective signal level of the image pickup sensor generated on a line including the defect-generating position and in parallel with the one direction is corrected. As a result of the foregoing process, a display failure is precisely corrected.

Abstract: An image processing device according to the present invention comprises an image signal operation unit, a correction data operation unit and a correcting unit. The image signal operation unit adjusts a white balance of an image signal by controlling a gain of the image signal for each color constituting the image signal. The correction data operation unit creates correction data for correcting an output of the image signal operation unit. The correcting unit further corrects the output of the image signal operation unit based on the correction data created by the correction data operation unit. According to the present invention, the white balance can be appropriately adjusted without losing subtle shades and shadows of a photographic object even in the case of an image signal including a noise level of a dark current.

Abstract: A focus adjusting method for focusing a focus of a digital camera comprises an image signal converting step in which an imaging light entering an optical lens mechanism is converted into an image signal, an extracting step in which a high-frequency component of the image signal is selectively extracted, a signal generating step in which a luminance signal and a color difference signal are generated from the high-frequency component of the image signal selectively extracted, and a focus adjusting step in which a focusing position of the optical lens mechanism is adjusted using a high-frequency component of the luminance signal. According to the foregoing constitution, a focus adjustment can be realized with a high accuracy and at a high speed.

Abstract: A multi-chip module is implemented by connecting a plurality of connection pads provided on, for example, two semiconductor chips via a plurality of conductive connecting members. To carry out a test for determining the quality of the connection between the two semiconductor chips, the multi-chip module is further provided with a plurality of switch elements so that the plurality of connecting members can be electrically conducted in a serial manner via the connection pads of the semiconductor chips. During the connection test, all the switch elements are turned on, and the impedance between both ends of the line including the plurality of connecting members conducted in a serial manner is measured using two probing pads.

Abstract: A solid-state image sensing apparatus including a solid-state image sensing device and a signal processing circuit. The solid-state image sensing device includes: a vertical transfer unit, composed of transfer columns corresponding to columns of the light-to-electric conversion elements, operable to transfer, in a vertical direction, signal charges read out from the light-to-electric conversion elements; a horizontal transfer unit operable to receive the signal charges from the vertical transfer unit and transfer them in a horizontal direction. The signal processing circuit converts the signal charges from the horizontal transfer unit into pixel data, and rearranges it into a two-dimensional array. In the rearrangement, the signal processing circuit, per transfer of one piece of pixel data, cyclically selects a line memory out of three line memories, writes a piece of pixel data into the selected line memory, or reads a row of pixel data from the selected line memory.

Abstract: A large chip includes a first set of branch wires that branch off from a first trunk wire and extend to respective wires so as to be connected to respective bond pads. Each of the branch wires of the first set includes a connection control element and a resistor. A small chip includes a second set of branch wires that branch off from a second trunk wire and extend to respective wires so as to be connected to respective bond pads. Each of the branch wires of the second set includes a connection control element and a resistor. Whether connection is properly made or not between the bond pads is determined by measuring a current value when voltage is applied to first and second test pads.

Abstract: A potential generating circuit comprises a capacitor (4); a ferroelectric capacitor (6) connected in series to the capacitor (4); an output terminal (11); a capacitor (10) for grounding the output terminal (11); a switch (9) for connecting a connecting node (5) between the two capacitors (4, 6) to the output terminal (11); and a switch (1) for connecting the connecting node (5) to the ground; wherein during a first period, with the switches (1) and (9) placed in the OFF state, a terminal (3) is provided with a positive potential and a terminal (7) is grounded; wherein during a second period following the first period, the terminal (3) is grounded and the switch (9) is placed in the ON state; wherein during a third period following the second period, the switch (9) is placed in the OFF state, the switch (1) is placed in the ON state, and the terminal (7) is provided with a positive potential; wherein during a fourth period following the third period, the terminal (7) is grounded; and wherein the first through

Abstract: A power supply voltage detection circuit includes a voltage division circuit for linearly dividing a power supply voltage, a reference voltage circuit for providing a reference voltage, and a comparison circuit for comparing the output voltage from the voltage division circuit and the reference voltage from the reference voltage circuit. The power supply voltage detection circuit outputs a signal upon detecting that the power supply voltage is equal to or higher than the reference voltage. A PMOS transistor is provided between the voltage division circuit and the comparison circuit. The PMOS transistor includes a source terminal connected to an output terminal of the voltage division circuit, a drain terminal connected to an input terminal of the comparison circuit, and a gate terminal connected to the ground.

Abstract: A power supply circuit according to the present invention is a power supply circuit formed on a semiconductor chip, including: an output transistor section outputting a power supply voltage; and a control circuit for controlling the output transistor section. The output transistor section is arranged in the vicinity of an external input/output terminal of the semiconductor chip.

Abstract: A bare-chip IP of a multi-chip module and an external device of the multi-chip module are interfaced with each other through a dedicated I/O bare-chip IP. Each of the bare-chip IPs other than the dedicated I/O bare-chip IP is not provided with an interface circuit for connection to the external device, and thus is only required to have a withstand voltage characteristic corresponding to the operating voltage of an internal circuit. As a result, it is only necessary to provide, on the bare-chip IPs, transistors of a few kinds of withstand voltage characteristics.

Abstract: A potential generating circuit comprises a capacitor (4); a ferroelectric capacitor (6) connected in series to the capacitor (4); an output terminal (11); a capacitor (10) for grounding the output terminal (11); a switch (9) for connecting a connecting node (5) between the two capacitors (4, 6) to the output terminal (11); and a switch (1) for connecting the connecting node (5) to the ground; wherein during a first period, with the switches (1) and (9) placed in the OFF state, a terminal (3) is provided with a positive potential and a terminal (7) is grounded; wherein during a second period following the first period, the terminal (3) is grounded and the switch (9) is placed in the ON state; wherein during a third period following the second period, the switch (9) is placed in the OFF state, the switch (1) is placed in the ON state, and the terminal (7) is provided with a positive potential; wherein during a fourth period following the third period, the terminal (7) is grounded; and wherein the first through

Abstract: A multi-chip module is implemented by connecting a plurality of connection pads provided on, for example, two semiconductor chips via a plurality of conductive connecting members. To carry out a test for determining the quality of the connection between the two semiconductor chips, the multi-chip module is further provided with a plurality of switch elements so that the plurality of connecting members can be electrically conducted in a serial manner via the connection pads of the semiconductor chips. During the connection test, all the switch elements are turned on, and the impedance between both ends of the line including the plurality of connecting members conducted in a serial manner is measured using two probing pads.

Abstract: During an intermittent operation mode, a switch is normally opened and a capacitor with a large capacitance is isolated from a circuit. Under this condition, a power source voltage is intermittently supplied to a driven device. Since a charge/discharge current of the capacitor during the intermittent operation mode is limited to the charge/discharge current of the capacitor with a small capacitance, the power consumption can be lowered. In addition, since no switch exists in the current path from a power source voltage conversion circuit to the driven device, there is no drop, due to a switch, in the voltage supplied from the power source voltage conversion circuit to the driven device. On the other hand, during a continuous operation mode in which power source voltage is continuously provided to the driven device, the switch is normally closed and a capacitor with a large capacitance is connected to the power source system. Then the noise level in the supplied power is lowered.

Abstract: A power supply device is provided in which, in order to increase a rise speed of an output voltage and to suppress a voltage drop when switching between power supply devices, during a second operation mode in which power supply is stopped, an output switch is turned off and a reference voltage generating circuit applies a reference voltage Vref2, which equals a gate voltage in a steady state during power supply (first operation mode), to the gate of an output transistor. Thus, when entering the first operation mode, the feedback operation of a differential operational amplifier quickly reaches a steady state. In addition, during the second operation mode, a switch that supplies power to the reference voltage generating circuit and the differential operational amplifier is open, reducing the power consumption of the power supply device itself.

Abstract: A large chip includes a first set of branch wires that branch off from a first trunk wire and extend to respective wires so as to be connected to respective bond pads. Each of the branch wires of the first set includes a connection control element and a resistor. A small chip includes a second set of branch wires that branch off from a second trunk wire and extend to respective wires so as to be connected to respective bond pads. Each of the branch wires of the second set includes a connection control element and a resistor. Whether connection is properly made or not between the bond pads is determined by measuring a current value when voltage is applied to first and second test pads.

Abstract: A cell library database includes function information of standard cells which are basic circuits forming a logical device, each of the standard cell comprising at least one of power supply terminal as logical terminals, the function information of the standard cell containing logical information or delay information of the power supply terminal relative to an output terminal, or function information of macro cells which are functional circuits forming a logical device, each of the macro cell comprising at least one of power supply terminals as logical terminals, the function information of the macro cell containing logical information or delay information of said power supply terminals relative to an output terminal. A design aiding system uses the cell library database to execute logical simulation, etc.