Patents by Inventor Jun Kajiwara

Jun Kajiwara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020149034
    Abstract: A bare-chip IP of a multi-chip module and an external device of the multi-chip module are interfaced with each other through a dedicated I/O bare-chip IP. Each of the bare-chip IPs other than the dedicated I/O bare-chip IP is not provided with an interface circuit for connection to the external device, and thus is only required to have a withstand voltage characteristic corresponding to the operating voltage of an internal circuit. As a result, it is only necessary to provide, on the bare-chip IPs, transistors of a few kinds of withstand voltage characteristics.
    Type: Application
    Filed: March 14, 2002
    Publication date: October 17, 2002
    Inventors: Shiro Sakiyama, Jun Kajiwara, Masayoshi Kinoshita
  • Patent number: 6462427
    Abstract: Each bare-chip IP includes pad electrodes that are of the same size and shape, made of the same material, and arranged in an array at the same pitch over almost the entire surface thereof. A silicon wiring substrate includes pad electrodes that are arranged in an array over almost the entire surface thereof at the same pitch as that between the pad electrodes of the bare-chip IPs. The bare-chip IPs are mounted on the silicon wiring substrate, thereby making a multichip module.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: October 8, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shiro Sakiyama, Jun Kajiwara, Masayoshi Kinoshita
  • Patent number: 6460168
    Abstract: A power supply circuit according to the present invention is a power supply circuit formed on a semiconductor chip, including: an output transistor section outputting a power supply voltage; and a control circuit for controlling the output transistor section. The output transistor section is arranged in the vicinity of an external input/output terminal of the semiconductor chip.
    Type: Grant
    Filed: March 27, 2000
    Date of Patent: October 1, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akira Yamamoto, Shirou Sakiyama, Hiroyuki Nakahira, Masayoshi Kinoshita, Katsuji Satomi, Jun Kajiwara, Shinichi Yamamoto
  • Patent number: 6429633
    Abstract: In a switching regulator, switching noise is reduced with keeping high conversion efficiency. The switching regulator includes plural output switching transistors 21 through 23 having different on-resistances, which are operated nadescending order of on-resistance in the on operation and are operated in an ascending order of on-resistance in the off operation. In this manner, abrupt current change can be suppressed in the switching operation, resulting in reducing di/dt noise derived from a parasitic inductor 102.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: August 6, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Jun Kajiwara, Katsuji Satomi, Shiro Sakiyama, Masayoshi Kinoshita, Katsuhiro Ootani
  • Publication number: 20020101263
    Abstract: A power supply voltage detection circuit includes a voltage division circuit for linearly dividing a power supply voltage, a reference voltage circuit for providing a reference voltage, and a comparison circuit for comparing the output voltage from the voltage division circuit and the reference voltage from the reference voltage circuit. The power supply voltage detection circuit outputs a signal upon detecting that the power supply voltage is equal to or higher than the reference voltage. A PMOS transistor is provided between the voltage division circuit and the comparison circuit. The PMOS transistor includes a source terminal connected to an output terminal of the voltage division circuit, a drain terminal connected to an input terminal of the comparison circuit, and a gate terminal connected to the ground.
    Type: Application
    Filed: January 24, 2002
    Publication date: August 1, 2002
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masayoshi Kinoshita, Jun Kajiwara, Shiro Sakiyama
  • Publication number: 20020079591
    Abstract: Each bare-chip IP includes pad electrodes that are of the same size and shape, made of the same material, and arranged in an array at the same pitch over almost the entire surface thereof. A silicon wiring substrate includes pad electrodes that are arranged in an array over almost the entire surface thereof at the same pitch as that between the pad electrodes of the bare-chip IPs. The bare-chip IPs are mounted on the silicon wiring substrate, thereby making a multichip module.
    Type: Application
    Filed: December 21, 2001
    Publication date: June 27, 2002
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shiro Sakiyama, Jun Kajiwara, Masayoshi Kinoshita
  • Publication number: 20020053897
    Abstract: In a switching regulator, switching noise is reduced with keeping high conversion efficiency. The switching regulator includes plural output switching transistors 21 through 23 having different on-resistances, which are operated in a descending order of on-resistance in the on operation and are operated in an ascending order of on-resistance in the off operation. In this manner, abrupt current change can be suppressed in the switching operation, resulting in reducing di/dt noise derived from a parasitic inductor 102.
    Type: Application
    Filed: April 28, 2000
    Publication date: May 9, 2002
    Inventors: JUN KAJIWARA, KATSUJI SATOMI, SHIRO SAKIYAMA, MASAYOSHI KINOSHITA, KATSUHIRO OOTANI
  • Publication number: 20020042902
    Abstract: A power supply circuit according to the present invention is a power supply circuit formed on a semiconductor chip, including: an output transistor section outputting a power supply voltage; and a control circuit for controlling the output transistor section. The output transistor section is arranged in the vicinity of an external input/output terminal of the semiconductor chip.
    Type: Application
    Filed: November 5, 2001
    Publication date: April 11, 2002
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akira Yamamoto, Shirou Sakiyama, Hiroyuki Nakahira, Masayoshi Kinoshita, Katsuji Satomi, Jun Kajiwara, Shinichi Yamamoto
  • Publication number: 20020030474
    Abstract: During an intermittent operation mode, a switch is normally opened and a capacitor with a large capacitance is isolated from a circuit. Under this condition, a power source voltage is intermittently supplied to a driven device. Since a charge/discharge current of the capacitor during the intermittent operation mode is limited to the charge/discharge current of the capacitor with a small capacitance, the power consumption can be lowered. In addition, since no switch exists in the current path from a power source voltage conversion circuit to the driven device, there is no drop, due to a switch, in the voltage supplied from the power source voltage conversion circuit to the driven device. On the other hand, during a continuous operation mode in which power source voltage is continuously provided to the driven device, the switch is normally closed and a capacitor with a large capacitance is connected to the power source system. Then the noise level in the supplied power is lowered.
    Type: Application
    Filed: August 3, 2001
    Publication date: March 14, 2002
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Shiro Sakiyama, Jun Kajiwara, Masayoshi Kinoshita
  • Patent number: 6307360
    Abstract: The switching regulator of a synchronous rectifying mode comprises the first and second switches SW1, SW2 arranged in series between the power source Vdd and the ground Vss, the switch control unit 1 which controls the on-off operation of the switches SW1, SW2, and the smoothing circuit 4 which smoothes the output node potential Vnd. When the signal Sc1 indicates that the output node potential Vnd goes below the first reference potential Vr1 which is the reference to detect the occurrence of the inrush current while the first switch SW1 is in the ON state, the control circuit 10 turns off the first switch SW1. Thus, the detection of the inrush current is conducted by making use of a voltage drop due to the on resistance of the first switch SW1, so that it is unnecessary to provide a resistance element for detecting the inrush current.
    Type: Grant
    Filed: October 23, 2000
    Date of Patent: October 23, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Jun Kajiwara, Shiro Sakiyama, Masayoshi Kinoshita, Katsuji Satomi, Katsuhiro Ootani
  • Patent number: 6150800
    Abstract: A power circuit including means for preventing the generation of an inrush current during the power circuit's initial operation without increasing the size of the power circuit is described. The power circuit comprises an output transistor for supplying a current from a power supply to an output terminal, and a differential amplifier for controlling the current supplied by the output transistor in such a manner as to regulate a voltage at the output terminal based on a preset reference voltage. A limiting transistor is provided as a source follower on a current path at the output stage of the differential amplifier. The gate potential of the output transistor is controlled using the source potential of the limiting transistor. Before the power circuit starts to operate, an operation controller charges a capacitor to control the gate potential of the limiting transistor so that during the initial operation of the power circuit, the capacitor is discharged by using a current source.
    Type: Grant
    Filed: September 15, 1999
    Date of Patent: November 21, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masayoshi Kinoshita, Shiro Sakiyama, Jun Kajiwara, Katsuji Satomi, Hiroo Yamamoto, Katsuhiro Ootani