Abstract: A Fresnel lens-integrated optical fiber that can be easily aligned and manufactured in miniature, and a method of fabricating the same are provided. The Fresnel lens-integrated optical fiber includes a light transmission section transmitting incident light, a light expansion section coupled to the light transmission section and expanding light provided from the light transmission section, and a Fresnel lens surface formed on a section of the light expansion section and focusing by passing through the light expanded in the light expansion section at a predetermined focal length. Accordingly, since the Fresnel lens surface has no curvature, arrangement of an optical coupling system is easy, manufacture is easy, and the optical coupling system can be miniaturized.

Abstract: A method for forming a tungsten film includes forming a tungsten nucleation layer having an amorphous-phase or a ?-phase over a semiconductor substrate. A first tungsten layer having a crystalline ?-phase is then formed over the tungsten nucleation layer to form a low resistivity tungsten film. A second tungsten layer is formed over the first tungsten layer by a physical vapor deposition process, and the second tungsten layer has a large grain size similar to that of the low resistivity tungsten film. The tungsten film has both good surface roughness and low resistivity, thus enhancing the production yield and reliability of a semiconductor device.

Abstract: A semiconductor device is made by forming patterns on a semiconductor substrate. After forming the patterns, sequentially forming a spacer layer, an oxidation promotion layer and a buffer layer on the semiconductor substrate including the surfaces of the patterns previously formed. An insulation layer is then formed on the buffer layer to fill the patterns. The semiconductor substrate including the insulation layer is subsequently annealed such that the buffer layer is oxidized and the insulation layer is baked.

Abstract: A transistor of a semiconductor device includes a substrate, a gate over the substrate, a source/drain region formed in the substrate to have a channel region therebetween, and an epitaxial layer formed below the channel region to have a different lattice constant from the substrate. The epitaxial layer having a different lattice constant with a substrate material is formed below the channel region to apply a stress to the channel region. Thus, the mobility of carriers of the transistor increases.

Abstract: A semiconductor device capable of selectively applying different stresses for increasing current drivability of PMOS transistor is made by defining trenches in a semiconductor substrate having a PMOS region; forming selectively a buffer layer on sidewalls of the trenches; forming an insulation layer to fill the trenches; annealing the semiconductor substrate such that compressive stress is applied in a channel length direction of a PMOS transistor by oxidizing the buffer layer; removing portions of the insulation layer and thereby forming an isolation layer; and forming the PMOS transistor on the PMOS region of the semiconductor substrate.

Abstract: The present invention relates to a laser-rotating arc hybrid welding system and a welding method using the system. The laser-rotating arc hybrid welding system of the present invention includes an arc discharge unit (2) for generating arc discharge along an area to be welded. A laser generation unit (4) radiates laser light onto the area to be welded. A rotating device (24) rotates the arc discharge unit (2). In the welding method using the laser-rotating arc hybrid welding system, a plurality of parent metals is aligned with a welding location. A laser-rotating arc hybrid welding system is located with respect to an area to be welded, arc discharge is generated while an arc discharge unit is rotated at a predetermined turning radius, and laser light is subsequently radiated using a laser generation unit.

Abstract: The present invention provides a method for fabricating a semiconductor device capable of preventing a contact resistance from increasing in a region contacted to an N-type conductive region during forming a conductive pattern directly contacted to the N-type conductive region including a conductive pattern and silicon, and preventing an increase in a parasitic capacity of the conductive pattern according to an increase in a thickness of a barrier layer.

Abstract: Disclosed is a method for forming a metal wiring in a semiconductor device in order to improve the operational speed of the semiconductor device. The method includes the steps of depositing an interlayer dielectric film on a silicon substrate, in which the interlayer dielectric film has a contact hole for exposing a predetermined portion of the silicon substrate, depositing a barrier layer on the interlayer dielectric film having the contact hole, depositing a first tungsten layer on the barrier layer by using SiH4 as a reaction gas, depositing a second tungsten layer on the first tungsten layer by using B2H6 as a reaction gas, depositing a third tungsten layer on the second tungsten layer in such a manner that the contact hole is filled with the third tungsten layer, and selectively etching the third tungsten layer, the second tungsten layer, the first tungsten layer, and the barrier layer, thereby forming the metal wiring.

Abstract: Disclosed are a transistor and a method for fabricating the same capable of increasing a threshold voltage and a driving current of the transistor. The method includes the steps of forming a first etch mask on a silicon substrate, forming a trench by etching the exposed isolation area, forming a first insulation layer in the trench and the first etch mask, forming a second insulation layer on the first insulation layer, removing the second insulation layer and the first insulation layer until the first etch mask is exposed, forming a trench type isolation layer on the isolation area, forming a second etch mask on an entire surface of the silicon substrate, etching the exposed channel area, performing an etching process with respect to a resultant substrate structure, and forming a gate in the recess.

Abstract: The present invention provides a method for fabricating a semiconductor device capable of preventing a contact resistance from increasing in a region contacted to an N-type conductive region during forming a conductive pattern directly contacted to the N-type conductive region including a conductive pattern and silicon, and preventing an increase in a parasitic capacity of the conductive pattern according to an increase in a thickness of a barrier layer.

Abstract: A separating region and a method of forming a separating region of a semiconductor device is provided that increases reliability of the device by isolating respective gate electrodes. The separating region and method prevent voids from being formed within a trench of the separating region. The method of forming the separating region includes forming patterns of first insulating layers on a semiconductor substrate by selectively etching the first insulating layers to have at least one opening disposed in a defined region of the semiconductor substrate, forming side walls of a second insulating layer on both lateral sides of the patterns of the first insulating layers, and etching the side walls of the second insulating layer and the exposed semiconductor substrate using the patterns of the first insulating layers as a mask to form trenches in the semiconductor substrate. Since a selectively ratio of the sidewalls and the semiconductor substrate is preferably 1:1, the trenches have a prescribed shape and depth.

Abstract: A method for fabricating an integrated circuit includes the steps of forming an isolating insulation film on a portion of a semiconductor substrate, forming a gate insulating film, a first conductive layer, an insulating film and a second conductive layer successively on the semiconductor substrate including the isolating insulation film, selectively removing the second conductive layer and the insulating film to pattern an upper electrode of a capacitor in a capacitor forming region and a dummy gate electrode in a transistor forming region, respectively, forming a lower electrode mask in the capacitor forming region, and selectively removing the first conductive layer and the gate insulating film by using the lower electrode mask and the dummy gate electrode as masks, to form a lower electrode of the capacitor and the gate electrode of the transistor.

Abstract: The present invention relates to a method of forming an interconnection for a semiconductor device using copper. The method of the invention, including the steps of forming an insulating layer having a groove on a semiconductor substrate containing active elements; forming and depositing a copper thin film on the insulating layer including the groove; and reflowing the copper thin film, may reflow the copper thin film deposited on the semiconductor substrate having a high-step surface for less than 30 min. below 450.degree. C., which show improved annealing conditions as compared with the conventional art. In addition, by reducing consumption of thermal energy in accordance with a low-temperature process, copper is restrained from being rapidly diffused through a silicon substrate, electrodes, etc. when forming the interconnection for the semiconductor device, thus improving productivity of the semiconductor devices.

Abstract: A method for fabricating wiring of a semiconductor device, which includes a first step for depositing an insulating film on a semiconductor substrate, and forming contact holes by selectively etching the insulating film, a second step for forming a barrier layer on the insulating film and the substrate, a third step for forming a first aluminum alloy layer on the barrier layer, a fourth step for forming a second aluminum alloy layer containing germanium on the first aluminum alloy layer, and a fifth step for forming an aluminum alloy wiring by annealing the substrate on which the first and the second aluminum alloy layers are formed, whereby making it possible to obtain the wiring of a semiconductor device capable of flowing at a low temperature which is the characteristic of Al--Ge wiring and capable of improving the characteristic of the electromigration of the wiring.

Abstract: A method for forming a wiring layer for a semiconductor device is disclosed. During the formation of a VLSI-scale device having a contact hole with a large aspect ratio, metal layers are filled into the contact hole without spatial discontinuities, and a first wiring metal deposition process is carried out by applying a chemical vapor deposition (CVD) process. Compared with a conventional method, even if a thin film of aluminum is deposited, the wiring metal film can be deposited into the contact hole without spatial discontinuities. The upper opening of the contact hole may remain wide after deposition of the first wiring layer, and the wiring metal atoms may easily move into the contact hole upon reaching the wafer during a second wiring metal deposition. The disclosed invention may provide for superior wiring metal filling characteristics as compared with conventional methods.