Abstract: In one embodiment of the invention, a method of simulating a circuit is disclosed including partitioning a circuit into a plurality of blocks, each of the plurality of blocks being radio-frequency blocks or non-radio frequency blocks; performing a first simulation of a first simulation type with the radio-frequency blocks to generate output waveforms of the radio-frequency blocks; performing a second simulation of a second simulation type with the non-radio-frequency blocks to generate output waveforms of the non-radio-frequency blocks where the second simulation type differs from the first simulation type; and synchronizing the first simulation and the second simulation together at one or more time steps to generate output waveforms for the circuit.

Abstract: A computer implemented method is provided for use in evaluating a hierarchical representation of a circuit design encoded in a computer readable medium comprising: traversing a circuit path within a higher level circuit that includes a reference potential connection, to identify a port of a call to a first lower level circuit that is DC path connected to the reference potential; identifying a first DC port group that includes each port of the call to the first lower level circuit that is DC path connected to the identified port of the call to the first lower level circuit; automatically marking as DC path connected to the reference potential, each port of the call to the first lower level circuit that is a member of the first DC port group; and traversing a circuit path within the first lower level circuit to identify a circuit path within the first lower level circuit that is DC path connected to a marked port of the first lower level circuit.

Abstract: Method and system for partitioning integrated circuits are disclosed. The method includes receiving a netlist representation of the circuit comprising circuit components, partitioning the circuit to form one or more circuit partitions according to a predefined partitioning method, where each circuit partition includes one or more circuit components. The method further includes, for each circuit partition, identifying substantial correlations between the circuit partition and one or more other circuit partitions to form a spanning tree, where the spanning tree connects the circuit partition to the one or more other circuit partitions via a graph, and merging the circuit partition and the one or more other circuit partitions in the spanning tree to form a new circuit partition.

Abstract: System and method for validating a circuit for simulation are disclosed. The system includes at least one processing unit for executing computer programs, a graphical user interface for viewing representations of the circuit on a display, a memory for storing information of the circuit, and logic for representing the circuit in a hierarchical data structure, where the hierarchical data structure has a plurality of subcircuits arranged in a connected graph, and where each subcircuit has circuit elements and one or more input and output ports. The system further includes logic for traversing the hierarchical data structure in a bottom-up fashion, logic for recording input port to output port (port-to-port) properties of the subcircuits in the hierarchical data structure, logic for traversing the hierarchical data structure in a top-down fashion, and logic for identifying illegal port paths using the port-to-port properties of the subcircuits.

Abstract: A computer implemented method is provided for use in evaluating a hierarchical representation of a circuit design encoded in a computer readable medium comprising: traversing a circuit path within a higher level circuit that includes a reference potential connection, to identify a port of a call to a first lower level circuit that is DC path connected to the reference potential; identifying a first DC port group that includes each port of the call to the first lower level circuit that is DC path connected to the identified port of the call to the first lower level circuit; automatically marking as DC path connected to the reference potential, each port of the call to the first lower level circuit that is a member of the first DC port group; and traversing a circuit path within the first lower level circuit to identify a circuit path within the first lower level circuit that is DC path connected to a marked port of the first lower level circuit.

Abstract: A system for communicating simulation solutions between circuit components in a hierarchical data structure includes a simulator module having one or more computer programs for representing the circuit as a hierarchically arranged set of branches, which includes a root branch and a plurality of other branches logically organized in a graph. The hierarchically arranged set of branches includes a first branch that contains one or more driver leaf circuits and a second branch that also contains one or more receiver leaf circuits, where the first branch and second branch are interconnected in the graph through a third branch at a higher hierarchical level in the graph than the first and second branches.

Abstract: A system for dynamically compressing circuit components during simulating of a circuit having a hierarchical data structure includes a simulator module having one or more computer programs for 1) selecting a group of leaf circuits from the first and second branches for simulation, 2) if two or more leaf circuits of the circuit having a substantially same isomorphic behavior, representing the two or more leaf circuits as a merged leaf circuit, 3) creating a first port connectivity interface dynamically for the group of leaf circuits in response to the merged leaf circuit, where the first port connectivity interface communicates changes in signal conditions among the group of leaf circuits, and 4) simulating the group of leaf circuits in accordance with the first port connectivity interface.

Abstract: A system for supporting multi-rate simulation of a circuit having a hierarchical data structure includes a simulator module having one or more computer programs for 1) partitioning the circuit into a plurality of group circuits, each group circuit includes one or more leaf circuits, where each leaf circuit produces a predictable set of output signals with a given set of input signals, 2) storing the group circuits in a scheduled event queue in accordance with priority in time which the group circuits need to be simulated, 3) retrieving from the scheduled event queue a set of group circuits for simulation within a predetermined time period, 4) distributing the set of group circuits into a set of predefined event lists, where each of the predefined event list stores one or more group circuits of a corresponding event type, and 5) simulating the one or more group circuits in each of the predefined event list in accordance with a rate of change of signal conditions of each individual group circuit.

Abstract: A method of transforming a first topology to a reduced topology is disclosed. One preferred embodiment of the present invention includes a method of transforming a circuit from a first topology to a reduced topology, said first topology comprising a plurality of inter-connected circuit elements. The method comprises the steps of: (a) identifying one or more circuit elements; (b) analyzing the effect of reducing one or more of said identified circuit elements on the topological and physical characteristics of said circuit; and (c) if the effect satisfies a first standard, generating a second topology reflecting the reduction of one or more identified circuit elements.

Abstract: Disclosed are a Viterbi decoding method and apparatus for high speed data transmissions. Branch metric is used with data inputted from a Viterbi decoder used in a communication system, and, when current state metric is used for addition, comparison, and selection, the selection operation is performed after simultaneous addition and comparison operations are performed, so that a faster decoding processing speed is obtained. The decoding process is carried out at a high speed with the addition and comparison operations carried out simultaneously, thereby preventing the increase of power consumption.

Abstract: The present invention relates to a plasma display apparatus comprising a panel; one or more drivers applying a driving voltage to a plurality of electrodes formed in the panel; and a control board supplying a control signal to the one or more drivers, wherein the control board includes an image signal processor which performs the digital conversion of a analog image signal inputted from the outside and a decoding. As at least one of the image signal processor which performs a decoding is integrated, the signal lines connected to the control board can be simply implemented such that the assembly production efficiency increases as well as the noise reduction in the signal transmission.

Abstract: System and method for validating a circuit for simulation are disclosed. The system includes at least one processing unit for executing computer programs, a graphical user interface for viewing representations of the circuit on a display, a memory for storing information of the circuit, and logic for representing the circuit in a hierarchical data structure, where the hierarchical data structure has a plurality of subcircuits arranged in a connected graph, and where each subcircuit has circuit elements and one or more input and output ports. The system further includes logic for traversing the hierarchical data structure in a bottom-up fashion, logic for recording input port to output port (port-to-port) properties of the subcircuits in the hierarchical data structure, logic for traversing the hierarchical data structure in a top-down fashion, and logic for identifying illegal port paths using the port-to-port properties of the subcircuits.

Abstract: A system for simulating a circuit having hierarchical data structure includes a simulator module having one or more computer programs for 1) creating a static database in accordance with a netlist description of the circuit, where the static database contains topology information of the circuit; 2) selecting a group circuit for simulation, where the group circuit contains one or more leaf circuits selected from the first branch and the second branch; 3) creating a dynamic database for representing the group circuit, where the dynamic database includes references to the static database for fetching topology information dynamically during simulation; and 4) simulating the group circuit in accordance with the dynamic database. Since the system duplicates and reproduces only the relevant dynamic information when necessary, the disclosed circuit simulator uses less memory and produces better performance.

Abstract: A system for adaptive partitioning of circuit components during simulating of a circuit having a hierarchical data structure includes a simulator module having one or more computer programs for 1) selecting a group of leaf circuits from the first branch and the second branch for simulation, where each leaf circuit is represented by a matrix comprising a set of equations, 2) determining a strength of coupling between two or more leaf circuits of the group in accordance with a set of predetermined electrical coupling criteria, 3) if two or more leaf circuits are deemed be strongly coupled, combining the corresponding matrix of each strongly coupled leaf circuit into a combined matrix, and 4) performing computation for the two or more strongly coupled leaf circuits in accordance with the combined matrix. The system adaptively adjusts the group circuit matrix for computing a group of circuits according to the strength of coupling between the circuits.

Abstract: The present invention relates generally to the field of design automation. More particularly, the present invention relates to a system and method for the modeling of circuit components for use by a simulator. The present invention includes a model of a circuit component having a plurality of properties that depend on at least two variables comprising: a space defined by the two or more variables; a partition of said space comprising a plurality of regions wherein at least two of the properties share said partition; and at least one definition representing at least one of the properties in at least one of the regions.