Patents by Inventor Jun Li

Jun Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240250698
    Abstract: This application discloses an encoding method, a decoding method, and an apparatus. The encoding method includes: obtaining a first bit sequence and a target code length M; then performing first channel encoding on the first bit sequence, to obtain a second bit sequence; performing second channel encoding based on the second bit sequence, to obtain a third bit sequence; and outputting the third bit sequence. The first bit sequence includes K information bits, the second bit sequence includes N bits, and the third bit sequence includes the N bits and E check bits, where M>N, and E=M?N. M, K, N, and E are all integers greater than or equal to 1.
    Type: Application
    Filed: March 28, 2024
    Publication date: July 25, 2024
    Inventors: Kangjian QIN, Rong LI, Huazi ZHANG, Xianbin WANG, Jun WANG
  • Publication number: 20240250697
    Abstract: An encoding method, a decoding method, and a communication apparatus. The communication apparatus obtains an information bit sequence with a length K. A length K1 of a first sequence based on K or M is determined, where M is a quantity of modulation symbols. A first vector is obtained based on K, K1, and a predefined sequence. A length of the first vector is 2JM, J is a modulation order, the first vector indicates J coding sub-blocks, the J coding sub-blocks separately belong to a first-type sub-block including at least one coding sub-block or a second-type sub-block including at least one coding sub-block. The communication apparatus determines frozen bit locations in the first-type sub-block and information bit locations in the second-type sub-block and encodes the information bit sequence based on the frozen bit locations in the first-type sub-block, the information bit locations in the second-type sub-block, and the first vector.
    Type: Application
    Filed: February 23, 2024
    Publication date: July 25, 2024
    Inventors: Xianbin WANG, Huazi ZHANG, Jiajie TONG, Rong LI, Jun WANG
  • Publication number: 20240246817
    Abstract: The present disclosure relates to the technical field of preparation of trisilylamine (TSA), in particular to a method for preparing TSA at an ultra-low temperature. The present disclosure provides a method for preparing TSA without a solvent at an ultra-low temperature, where by-products generated by a reaction can be easily removed by filtration with a metal ion-adsorption permeable membrane. The TSA obtained by the reaction has a gas chromatography (GC) purity of 99.5%, a receivable yield of not less than 85% (in terms of ammonia), and a metal ion purity of 6N. In addition, the method has a simple device, a high reaction degree of raw materials, a lower cost, a great market value, and a better industrial production benefit.
    Type: Application
    Filed: May 27, 2022
    Publication date: July 25, 2024
    Inventors: Wenhui Xiong, Qinqi Xu, Gang Chen, Jun Li, Guangdi Zhang, Huilong He, Xiaodong Zhang, Ping Li
  • Publication number: 20240245379
    Abstract: The present disclosure relates to a device and methods for clock synchronization. The device may include a first synchronization component and one or more second synchronization components. The first synchronization component may be configured to transmit a first synchronization signal to the one or more second synchronization components. Each second synchronization component of the one or more second synchronization components may be configured to generate a second synchronization signal based on the first synchronization signal and transmit the second synchronization signal to one or more detectors. The second synchronization signal may be configured to reset a clock of a detector of the one or more detectors corresponding to the each second synchronization component.
    Type: Application
    Filed: March 17, 2024
    Publication date: July 25, 2024
    Applicant: SHANGHAI UNITED IMAGING HEALTHCARE CO., LTD.
    Inventor: Jun LI
  • Publication number: 20240249659
    Abstract: A method and a circuit for driving a display panel, and a display device are disclosed. The display panel includes rows of sub-pixels. The method includes a display process, which includes: generating an initial driving signal for each row of sub-pixels according to image information of an image to be displayed; adjusting the initial driving signal for each row of sub-pixels according to a compensation gain of each row of sub-pixels, so as to obtain a target driving signal, the compensation gain of each row of sub-pixels is an actual brightness coefficient of the row of sub-pixels with respect to a reference row of sub-pixels during the display panel displaying an image with a test gray scale; and driving each row of sub-pixels to display according to the target driving signal for the row of sub-pixels, so as to enable each row of sub-pixels to reach target brightness.
    Type: Application
    Filed: February 28, 2022
    Publication date: July 25, 2024
    Inventors: Jianwei SUN, Liugang ZHOU, Jiao LIU, Jiantao LIU, Jun WANG, Yunyun LIANG, Qing LI
  • Publication number: 20240247569
    Abstract: Techniques for carbon sequestration and storage site selection are presented.
    Type: Application
    Filed: January 19, 2023
    Publication date: July 25, 2024
    Inventors: Jun Tao MA, Mengyu HAN, Jing WANG, Vincenzo DE GENNARO, Shao Yong SU, Bingtao LI, Pei YAN, Ye JI
  • Publication number: 20240250694
    Abstract: Embodiments of the present disclosure propose an Erasing-based Lossless Floating-point compression method, i.e., Elf. The main idea of Elf is to erase the last few bits (i.e., set them to zero) of floating-point values, so the XORed values are supposed to contain many trailing zeros, where the erased bits are determined based on the decimal place count and the digits on the exponent bits.
    Type: Application
    Filed: April 27, 2023
    Publication date: July 25, 2024
    Applicant: Chongqing University
    Inventors: Ruiyuan LI, Jun JIANG, Chao CHEN, Dongxia ZHANG, Zheng LI, Yi WU
  • Patent number: 12042997
    Abstract: An automatic leveling device of a 3D printer, and a 3D printer is provided. The automatic leveling device includes a photoelectric switch, an electromagnetic assembly and a probe assembly. The photoelectric switch is arranged in a housing and defines a photosensitive groove. The electromagnetic assembly is arranged in the housing and defines a sliding hole. The probe assembly is slidably engaged in the sliding hole, and an end of the probe assembly is engaged in the photosensitive groove. The electromagnetic assembly is capable of driving the probe assembly to make the end of the probe assembly move out of the photosensitive groove. The automatic leveling device has the advantages of simple structure, low manufacturing difficulty, low production cost, simple and stable leveling mode, high detection repetition accuracy and no complex circuit and software cooperation.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: July 23, 2024
    Assignee: Shenzhen Creality 3D Technology Co., Ltd.
    Inventors: Hui-Lin Liu, Jing-Ke Tang, Chun Chen, Dan-Jun Ao, Peng-Jian Li, Bin Qiao, Pin Chen
  • Patent number: 12042897
    Abstract: The present disclosure provides a grinding wheel cutting apparatus comprising a first laser distance sensor, a master controller and a grinding wheel. The first laser distance sensor is communicatively coupled to the master controller. The laser distance sensor is configured to obtain an outer diameter of a rod workpiece. The master controller is configured to determine a segment length of a segment to be cut from the rod workpiece based on the outer diameter, a material density of the rod workpiece and a preset segment weight. The master controller is configured to perform a control to circularly cut the rod workpiece with the grinding wheel according to the segment length. The present disclosure further relates to a cutting method using the grinding wheel cutting apparatus.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: July 23, 2024
    Assignees: BIAM ALLOYS CO., LTD., JIUMA AUTOMATIC MACHINERY (SHANGHAI) CO., LTD.
    Inventors: Gang Liu, Xiafei Zhou, Yu Meng, Hongbo Li, Jun Gu, Xujie Wan
  • Patent number: 12046630
    Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure, and relates to the technical field of semiconductors. The manufacturing method includes: providing a base, wherein the base is provided with an active region; forming a gate layer on the base; forming isolation structures on a periphery of the gate layer, wherein in a direction away from the gate layer, each of the isolation structures at least includes a hollow portion and an isolation portion; forming an insulating structure on top surfaces of the isolation structures; forming contact plugs, wherein the contact plugs penetrate the insulating structure; an end of each of the contact plugs close to the base is electrically connected to the active region; each of the contact plugs is located on a side of each of the isolation structures away from the gate layer.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: July 23, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Qiang Wan, Kangshu Zhan, Jun Xia, Sen Li, Penghui Xu, Tao Liu
  • Patent number: 12045142
    Abstract: A memory image can be captured by generating metadata indicative of a state of volatile memory and/or byte-addressable PMEM at a particular time during execution of a process by an application. This memory image can be persisted without copying the in-memory data into a separate persistent storage by storing the metadata and safekeeping the in-memory data in the volatile memory and/or PMEM. Metadata associated with multiple time-evolved memory images captured can be stored and managed using a linked index scheme. A linked index scheme can be configured in various ways including a full index and a difference-only index. The memory images can be used for various purposes including suspending and later resuming execution of the application process, restoring a failed application to a previous point in time, cloning an application, and recovering an application process to a most recent state in an application log.
    Type: Grant
    Filed: November 29, 2022
    Date of Patent: July 23, 2024
    Assignee: MEMVERGE, INC.
    Inventors: Ronald S. Niles, Yue Li, Jun Gan, Chenggong Fan, Robert W. Beauchamp
  • Patent number: 12046912
    Abstract: Embodiments of this application provide a wireless charger, and relate to the field of charging device technologies. The wireless charger includes a wireless charging module, a first fan, a housing including a contact plate used for contact with the rear surface of the terminal device, and an air intake vent disposed at a position that is of the housing and that is close to the first fan, and an airflow guide structure disposed on a side that is of the housing and that is adjacent to the contact plate. The airflow guide structure extends toward the display surface of the terminal device.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: July 23, 2024
    Inventors: Hao Wu, Quanming Li, Jun Chen, Li He
  • Patent number: 12046297
    Abstract: An apparatus that comprises a plurality of memory cells and a control circuit coupled to the plurality of memory cells is disclosed. The control circuit is configured to perform a read operation. The read operation includes determining a read condition of a memory cell, where the read condition is of a plurality of read conditions and determining a boost timing for the memory cell, where the boost timing corresponds to the read condition.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: July 23, 2024
    Assignee: SanDisk Technologies LLC
    Inventors: Peng Wang, Jia Li, Behrang Bagheri, Keyur Payak, Bo Lei, Long Pham, Jun Wan
  • Patent number: 12048139
    Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a substrate, where the substrate includes a complete die region and an incomplete die region; forming a stack on the substrate; forming a first mask layer with a first pattern on the stack; forming a first photoresist layer on the first mask layer; exposing the first photoresist layer, and developing to remove the first photoresist layer on the complete die region; and etching the stack by using the first mask layer on the complete die region and the first photoresist layer on the incomplete die region as masks.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: July 23, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Sen Li, Jun Xia
  • Patent number: 12047174
    Abstract: This application provides a signal transmission method and an apparatus. A network device broadcasts a navigation reference signal and a communication signal. A terminal device may determine its position information based on the navigation reference signal. A communication sequence in the communication signal and a navigation sequence in the navigation reference signal are coupled by using a same even-number-stage m-sequence, so that the terminal device is supported in completing an integrated communication and navigation function based on the broadcast signal.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: July 23, 2024
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yu Wang, Jianwei Zhou, Yunfei Qiao, Hejia Luo, Rong Li, Jun Wang
  • Patent number: 12048138
    Abstract: The present application provides a method for preparing a semiconductor structure and a semiconductor structure, relating to the technical field of semiconductors. The method for preparing a semiconductor structure includes: providing a base; forming a support layer having capacitor holes and electric contact structures; forming a first dielectric layer in the capacitor holes, the first dielectric layer surrounding first intermediate holes; forming a first electrode layer in the first intermediate holes, the first electrode layer filling the first intermediate holes; removing part of the support layer to form second intermediate holes; forming a second dielectric layer in the second intermediate holes, the first dielectric layer and the second dielectric layer forming a dielectric layer; and, forming a second electrode layer on the dielectric layer.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: July 23, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Kangshu Zhan, Qiang Wan, Penghui Xu, Tao Liu, Sen Li, Jun Xia
  • Publication number: 20240242656
    Abstract: A power supply circuit, a driving method thereof, a printed circuit board, a display module and a display apparatus are disclosed, which relates to a technical field of displaying. The power supply circuit includes a first power management chip and a second power management chip configured to be respectively connected with a display panel and provide different driving signals to the display panel, and the driving signals are configured for driving the display panel to display.
    Type: Application
    Filed: May 20, 2022
    Publication date: July 18, 2024
    Applicants: CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE Technology Group Co., Ltd.
    Inventors: Ying Zhang, Jin Sha, Can Shen, Xiang Fang, Bo Ran, Chao Gao, Yao Chen, Yiming Cheng, Jinxiang Li, Shifei Huang, Shengjie Yin, Pan Chen, Jun Tao, Wendi Zhang, Zhou Zhang, Qiuju Xie, Jun Wei, Hongchao Su
  • Publication number: 20240241831
    Abstract: Techniques to reduce data processing latency for a device. Circuitry at a device coupled with a host processor can facilitate execution of parallel tasks associated with processing data for a service offloaded to the device from the host processor. The parallel tasks can include prefetching information for address translations related to a shared virtual memory (SVM) space that is shared between the device and the host processor and prefetching data to be processed by device in relation to the offloaded service.
    Type: Application
    Filed: March 29, 2024
    Publication date: July 18, 2024
    Inventors: Junyuan WANG, Haoxiang SUN, Xin ZENG, Maksim LUKOSHKOV, Weigang LI, Zijuan FAN, Jun XU
  • Publication number: 20240240645
    Abstract: The present invention relates to a gas bearing for a centrifugal compressor, comprising a housing and a motor shaft located within the housing. The gas bearing comprises: a bearing housing, sleeved on an outer side of the motor shaft and fixed on the housing of the centrifugal compressor; an electromagnetic stator, fixed in or near the middle of the top of the bearing housing, and wound with a coil that can be powered; an electromagnetic rotor, fixed on an outer surface of the motor shaft and arranged circumferentially around the motor shaft; and a foil, located between the bearing housing and the motor shaft, and attached with a frication-resistant coating. The present invention further proposes a centrifugal compressor configured with the gas bearing, and a refrigeration system equipped with the centrifugal compressor.
    Type: Application
    Filed: January 17, 2024
    Publication date: July 18, 2024
    Inventors: Wei Zhang, Jiedong Li, Jun Cao, Caiyan Jin
  • Publication number: 20240243655
    Abstract: In a power factor correction PFC circuit control method and a PFC circuit, a control module determines that an alternating current on a single-phase input/output terminal is in a positive half cycle. The control module turns on or turns off switching transistors on the first bridge arm and the second bridge arm, to boost a first voltage at a first parallel connection point. The control module turns on a switching transistor on the third bridge arm when determining that the first voltage is equal to a voltage of a positive bus of the direct current module. A switching loss of the PFC circuit can be effectively reduced, and performance of the PFC circuit can be improved.
    Type: Application
    Filed: March 27, 2024
    Publication date: July 18, 2024
    Inventors: Xijun ZHANG, Xue ZHANG, Jun YAO, Qiya YANG, Hongfeng LIANG, Chao GAO, Yongchao LI