Patents by Inventor Jun Murata

Jun Murata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6077735
    Abstract: A method of making semiconductor devices which enables control of the impurity concentration and fine patterning by making removal of residual stress due LOCOS oxidation compatible with the formation of deep wells. A selective oxide layer is formed for separating element regions on a principal plane of a semiconductor substrate, for example, a p.sup.- -type silicon substrate 1. A mask is formed (for example photoresist 47) on the surface including the selective oxide layer and impurities (for example phosphorous) of a conductivity type opposite that of the semiconductor substrate are introduced via an opening in the mask. Then the selective oxide film is annealed by a high-temperature treatment while a deep well (for example n-type deep well 50) is formed by introducing the impurities.
    Type: Grant
    Filed: August 28, 1996
    Date of Patent: June 20, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Yuji Ezaki, Shinya Nishio, Fumiaki Saitoh, Hideo Nagasawa, Toshiyuki Kaeriyama, Songsu Cho, Hisao Asakura, Jun Murata, Yoshitaka Tadaki, Toshihiro Sekiguchi, Keizo Kawakita
  • Patent number: 6060352
    Abstract: A method for fabricating DRAMs each having a COB structure, and the semiconductor device formed by this method, are provided. In one embodiment, the word line and/or bit line is covered with an insulating film having a comparatively small etching rate. Contact holes are formed while being defined by those insulating films in self-alignment.
    Type: Grant
    Filed: January 28, 1998
    Date of Patent: May 9, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Toshihiro Sekiguchi, Hideo Aoki, Yoshitaka Tadaki, Keizo Kawakita, Jun Murata, Katsuo Yuhara, Michio Nishimura, Kazuhiko Saitoh, Minoru Ohtsuka, Masayuki Yasuda, Toshiyuki Kaeriyama, Songsu Cho
  • Patent number: 6041209
    Abstract: A charging member including an elastomeric member including an elastomeric material. The elastomeric material has a double oxide contained therein, the double oxide being a solid solution compound of oxides of at least two different metals formed by crystal lattice substitution. The at least two different metals have different valences, whereby the double oxide has an electroconductivity that is larger than that of either one of the oxides of at least two different metals when not in solution.
    Type: Grant
    Filed: April 24, 1998
    Date of Patent: March 21, 2000
    Assignee: Canon Kabushiki Kaisha
    Inventor: Jun Murata
  • Patent number: 6023084
    Abstract: A semiconductor memory device has a semiconductor substrate, and memory cells provided at intersections between word line conductors and bit line conductors. Adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which first semiconductor regions of the transistors of the adjacent two memory cells are united at their boundary into a single region and are connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the transistors of the adjacent two memory cells are connected to word line conductors adjacent to each other, respectively, and the second semiconductor regions of the transistors of the adjacent two memory cells are connected to the respective information storage capacitors.
    Type: Grant
    Filed: October 19, 1998
    Date of Patent: February 8, 2000
    Assignees: Hitachi, Ltd., Texas Instruments Inc.
    Inventors: Yoshitaka Tadaki, Jun Murata, Toshihiro Sekiguchi, Hideo Aoki, Keizo Kawakita, Hiroyuki Uchiyama, Michio Nishimura, Michio Tanaka, Yuji Ezaki, Kazuhiko Saitoh, Katsuo Yuhara, Songsu Cho
  • Patent number: 6023597
    Abstract: A cellular conductive roller has closed cells and open cells with conductive powder filling the open cells of the cellular conductive roller. A method for making a cellular conductive roller includes filling the open cells in the cellular conductive roller with conductive powder, adhering a tacky sheet to the surface of said cellular conductive roller; then peeling said tacky sheet off the surface of said cellular conductive roller. Also disclosed is an electrophotographic device using the cellular conductive roller and a process cartridge into which the cellular conductive roller is integrated.
    Type: Grant
    Filed: May 29, 1996
    Date of Patent: February 8, 2000
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroshi Mayuzumi, Yoshiaki Nishimura, Jun Murata, Nobutoshi Hayashi, Akiya Kume, Yukinori Nagata
  • Patent number: 6009714
    Abstract: A controller for an absorption cold/hot water generating machine, in which a refrigerating cycle is formed by pipe-connecting an evaporator, an absorber, a solution heat exchanger, a low-temperature generator, a condenser, and a high-temperature generator, and the solution level in a header of the high-temperature generator is kept within a prescribed range by controlling the flow rate of the solution fed from the absorber to the high-temperature generator; wherein a solution pump for feeding a solution from the absorber to the high-temperature generator is inverter-driven, and there is provided pressure difference detecting means for detecting a difference in pressure between the high-temperature generator and the absorber; and wherein there is provided control means which controls the solution pump driving frequency of the inverter as a function of a pressure difference between the high-temperature generator and the absorber.
    Type: Grant
    Filed: July 17, 1998
    Date of Patent: January 4, 2000
    Assignee: Ebara Corporation
    Inventors: Syouji Tanaka, Takashi Kaneko, Naoyuki Inoue, Jun Murata, Teruwo Shiraishi, Toshio Matsubara, Nobutaka Matsuda, Motonao Kera
  • Patent number: 6007746
    Abstract: A method for manufacturing preforms used in molding optical elements includes: (1) forming an array made from a material for optical elements, in which a plurality of preform portions used in molding optical elements are connected; (2) applying vibration to the outer peripheral part of the preform portion in the thickness direction of the array by a pair of punches; and then (3) punching the preform portions.
    Type: Grant
    Filed: November 7, 1997
    Date of Patent: December 28, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Jun Murata, Toshiaki Takano, Masaaki Sunohara
  • Patent number: 6001454
    Abstract: A charging member supplied with a voltage to charge a charge-receiving member such as an electrophotographic photosensitive member has an elastic layer of an ethylene-propylene copolymer containing a diene component. The ethylene-propylene copolymer has an iodine value of 23-32. The charging member is improved in resistance to permanent deformation while providing excellent images for a long period.
    Type: Grant
    Filed: August 1, 1997
    Date of Patent: December 14, 1999
    Assignee: Canon Kabushiki Kaisha
    Inventors: Jun Murata, Yoshiaki Nishimura, Hiroshi Mayuzumi
  • Patent number: 5965069
    Abstract: A method for making optical preforms of optical elements without residual stress or distortion is provided. In this method, an optical material is supplied between upper and lower molds. The upper mold has a plurality of recesses arranged in a predetermined pitch, and each recess corresponds to a first surface shape of the optical element. The lower mold has a plurality of recesses facing the recesses of the upper mold and each recess of the lower mold corresponds to a second surface shape of the optical element. The supplied optical material is pressed between the upper and lower molds to be a set of optical preforms. The set of optical preforms is processed by die punching or tool cutting to separate each optical preform from the set of optical preforms. Each optical preform is used for producing an optical element by further pressing. Alternatively, optical element can be formed directly by the press molding process.
    Type: Grant
    Filed: January 24, 1997
    Date of Patent: October 12, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Jun Murata, Takahisa Kondou, Masaaki Sunohara, Toshiaki Takano, Chizuo Izumino, Shoji Nakamura
  • Patent number: 5933724
    Abstract: A phase shifting mask is used for manufacturing a semiconductor integrated circuit device including a conductor pattern in which the line width of patterned conductor strips or the space between patterned conductor strips is not constant. For main transparent areas in the mask corresponding to the conductor pattern, auxiliary pattern segments are provided for compensating changes in the phase distribution of transmitted light caused by changes of the line width or the space. Alternately, the spaces between the conductor strips are adjusted to suppress the changes in the phase distribution of transmitted light. Whether the auxiliary pattern segments should have the phase shifting function is determined depending upon the disposition of the main transparent areas.
    Type: Grant
    Filed: August 26, 1996
    Date of Patent: August 3, 1999
    Assignees: Hitachi, Ltd., Texas Instruments
    Inventors: Toshihiro Sekiguchi, Yoshitaka Tadaki, Keizo Kawakita, Jun Murata, Katsuo Yuhara, Toshikazu Kumai, Michio Tanaka, Michio Nishimura, Kazuhiko Saitoh, Takatoshi Kakizaki, Takeshi Sakai, Toshiyuki Kaeriyama, Songsu Cho
  • Patent number: 5933726
    Abstract: A semiconductor device, such as a dynamic RAM, and method of making it. A number of stacked cell capacitors are placed at a prescribed spacing in an alignment direction on top of a p.sup.- -type silicon substrate (1). Each capacitor has a nearly perpendicular cylindrical lower electrode (cylindrical polysilicon layer (96)), a dielectric film (silicon nitride film (77)), and upper electrode (plate electrode (78) made of polysilicon). The spacing in the alignment direction is smaller than the inner diameter of the lower electrode.
    Type: Grant
    Filed: August 27, 1996
    Date of Patent: August 3, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Michio Nishimura, Kazuhiko Saitoh, Masayuki Yasuda, Takashi Hayakawa, Michio Tanaka, Yuji Ezaki, Katsuo Yuhara, Minoru Ohtsuka, Toshikazu Kumai, Songsu Cho, Toshiyuki Kaeriyama, Keizo Kawakita, Toshihiro Sekiguchi, Yoshitaka Tadaki, Jun Murata, Hideo Aoki, Akihiko Konno, Kiyomi Katsuyama, Takafumi Tokunaga, Yoshimi Torii
  • Patent number: 5930624
    Abstract: A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, is disclosed. In a first aspect, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry.
    Type: Grant
    Filed: January 26, 1998
    Date of Patent: July 27, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Jun Murata, Yoshitaka Tadaki, Isamu Asano, Mitsuaki Horiuchi, Jun Sugiura, Hiroko Kaneko, Shinji Shimizu, Atsushi Hiraiwa, Hidetsugu Ogishi, Masakazu Sagawa, Masami Ozawa, Toshihiro Sekiguchi
  • Patent number: 5917211
    Abstract: A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.
    Type: Grant
    Filed: November 25, 1997
    Date of Patent: June 29, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Jun Murata, Yoshitaka Tadaki, Hiroko Kaneko, Toshihiro Sekiguchi, Hiroyuki Uchiyama, Hisashi Nakamura, Toshio Maeda, Osamu Kasahara, Hiromichi Enami, Atsushi Ogishima, Masaki Nagao, Michimasa Funabashi, Yasuo Kiguchi, Masayuki Kojima, Atsuyoshi Koike, Hiroyuki Miyazawa, Masato Sadaoka, Kazuya Kadota, Tadashi Chikahara, Kazuo Nojiri, Yutaka Kobayashi
  • Patent number: 5889312
    Abstract: A semiconductor device includes a thermal oxide film for isolation, a semiconductor region that becomes an element forming region with the circumference thereof surrounded by the oxide film and diffused resistance layers in the semiconductor region and provides a structure for controlling resistance value variation of diffused resistors originated in a stress generated at time of forming the oxide film for isolation. A distance between an end portion on a longer side closest to a thermal oxide film of the diffused layer and an end of the thermal oxide film is apart from each other by a predetermined value determined by stress distribution in the semiconductor region or by at least 4 .mu.
    Type: Grant
    Filed: July 10, 1997
    Date of Patent: March 30, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Hideo Miura, Yasunobu Tanizaki, Eiji Wakimoto, Shinji Sakata, Makoto Ogasawara, Hiroo Masuda, Jun Murata, Noriaki Okamoto
  • Patent number: 5831300
    Abstract: A semiconductor memory device has a semiconductor substrate, word line conductors and bit line conductors, and memory cells provided at intersections between the word line conductors and bit line conductors. Adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which first semiconductor regions of the transistors of the adjacent two memory cells are united at their boundary into a single region and are connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the transistors of the adjacent two memory cells are connected to word line conductors adjacent to each other, respectively, the second semiconductor regions of the transistors of the adjacent two memory cells are connected to the respective information storage capacitors.
    Type: Grant
    Filed: October 16, 1996
    Date of Patent: November 3, 1998
    Assignees: Hitachi, Ltd., Texas Instruments Incorporated
    Inventors: Yoshitaka Tadaki, Jun Murata, Toshihiro Sekiguchi, Hideo Aoki, Keizo Kawakita, Hiroyuki Uchiyama, Michio Nishimura, Michio Tanaka, Yuji Ezaki, Kazuhiko Saitoh, Katsuo Yuhara, Songsu Cho
  • Patent number: 5824408
    Abstract: A white electroconductive coating composition includes a white pigment having a whiteness of at least 60, a white conductive material having a whiteness of at least 50 and a volume resistivity of at most 1.times.10.sup.10 ohm.cm. The coating composition is suitable to provide a a coating film showing a whiteness of at least 60 and a surface resistivity of at most 1.times.10.sup.11 ohm/cm.sup.2. Such a white conductive layer may be formed on a back side of a surface insulating film of a transfer material carrying member of an electrophotographic image forming apparatus to provide a reference white pattern for detecting a density of a toner image formed on the carrying member, thereby allowing controlled image formation based on the detected density data.
    Type: Grant
    Filed: April 26, 1996
    Date of Patent: October 20, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventors: Akiya Kume, Yoshiaki Nishimura, Jun Murata, Nobutoshi Hayashi, Yukinori Nagata, Hiroshi Mayuzumi
  • Patent number: 5819142
    Abstract: The present invention pertains to a charging member which is energized to charge a chargeable member by contact-electrification and which comprises a conductive elastic layer having a surface layer containing a polymer having a main chain containing a structural unit of the following formula:--O--(CH.sub.2).sub.n --O--CO--wherein n is an integer of from 4 to 10.With stable charging properties, the charging member of the present invention has relatively uniform surface resistance, little dependency on the environmental conditions, and decreased contamination of photosensitive bodies and the like.
    Type: Grant
    Filed: May 13, 1997
    Date of Patent: October 6, 1998
    Assignee: Canon Kaubshiki Kaisha
    Inventors: Jun Murata, Yoshiaki Nishimura, Akiya Kume, Hiroshi Mayuzumi
  • Patent number: 5804479
    Abstract: The etch-back amount of a silicon oxide film of a memory array which is a higher altitude portion is increased when etching back and flattening the silicon oxide film by arranging a first-layer wiring on a BPSG film covering an upper electrode of an information-storing capacitative element only in a peripheral circuit but not arranging it in the memory array.Thus, a DRAM having a stacked capacitor structure is obtained such that the level difference between the memory array and peripheral circuit is decreased, and the formation of wiring and connection holes are easy.
    Type: Grant
    Filed: August 9, 1996
    Date of Patent: September 8, 1998
    Assignees: Hitachi, Ltd., Texas Instruments Inc.
    Inventors: Hideo Aoki, Jun Murata, Yoshitaka Tadaki, Toshihiro Sekiguchi, Keizo Kawakita, Takashi Hayakawa, Katsutoshi Matsunaga, Kazuhiko Saitoh, Michio Nishimura, Minoru Ohtsuka, Katsuo Yuhara, Michio Tanaka, Yuji Ezaki, Toshiyuki Kaeriyama, SongSu Cho
  • Patent number: 5766753
    Abstract: The present invention pertains to an elastic member and a charging roller for electrophotography which are provided with an electrical semi-conductive elastic layer on a conductive body with an adhesive layer arranged between them. The adhesive layer contains carbon black and graphite at a total content of 20 to 80 phr as conductive fillers and also contains a thermoplastic elastomer as a binder. Disclosed is an electrophotographic device having an elastic member and an electrophotographic photosensitive body.
    Type: Grant
    Filed: December 22, 1995
    Date of Patent: June 16, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventors: Jun Murata, Yoshiaki Nishimura
  • Patent number: 5757508
    Abstract: A charging member including an elastomeric member including an elastomeric material. The elastomeric material includes a polymer dispersion medium having a double oxide dispersed therein, the double oxide being a solid solution compound of oxides of at least two different metals formed by crystal lattice substitution. The at least two different metals have different valences, whereby the double oxide has an electroconductivity that is larger than that of either one of the oxides of at least two different metals when not in solution. Also, the charging member has resistance stability in the semiconductive region.
    Type: Grant
    Filed: March 9, 1994
    Date of Patent: May 26, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventor: Jun Murata