Abstract: Embodiments of the invention provide a disk drive capable of writing information on data tracks even more positively when a shingle write method is adopted. In one embodiment, the disk drive is characterized in that, when information is to be written on a plurality of adjacent data tracks on a recording medium through the shingle write method, writing of information is controlled by detecting an actual writing position based on servo information recorded on the recording medium and determining whether or not the detected actual writing position meets a predetermined condition.

Abstract: A semiconductor circuit which includes one or plural fuse circuits being disconnectable and having a connected or disconnected state and a control circuit controlling a controlled circuit is provided. The control circuit controls the controlled circuit according to the state of the fuse circuit or the states of the fuse circuits when a normal mode is designated and controls the controlled circuit according to the state of the fuse circuit or the states of the fuse circuits and an input signal or input signals when a test mode is designated.

Abstract: Embodiments of the invention provide a disk drive capable of writing information on data tracks even more positively when a shingle write method is adopted. In one embodiment, the disk drive is characterized in that, when information is to be written on a plurality of adjacent data tracks on a recording medium through the shingle write method, writing of information is controlled by detecting an actual writing position based on servo information recorded on the recording medium and determining whether or not the detected actual writing position meets a predetermined condition.

Abstract: A semiconductor circuit which includes one or plural fuse circuits being disconnectable and having a connected or disconnected state and a control circuit controlling a controlled circuit is provided. The control circuit controls the controlled circuit according to the state of the fuse circuit or the states of the fuse circuits when a normal mode is designated and controls the controlled circuit according to the state of the fuse circuit or the states of the fuse circuits and an input signal or input signals when a test mode is designated.

Abstract: A semiconductor circuit which includes one or plural fuse circuits being disconnectable and having a connected or disconnected state and a control circuit controlling a controlled circuit is provided. The control circuit controls the controlled circuit according to the state of the fuse circuit or the states of the fuse circuits when a normal mode is designated and controls the controlled circuit according to the state of the fuse circuit or the states of the fuse circuits and an input signal or input signals when a test mode is designated.

Abstract: A semiconductor memory includes a refresh timer and an arbiter for determining the order of precedence between an access operation and a refresh operation, in order to automatically perform refresh operations inside the memory. A detecting circuit operates in a test mode and outputs a detection signal indicating that the refresh operation is yet to be performed, when a new internal refresh request occurs before the refresh operation is performed. For example, the detection signal is output when the interval of access requests is short and no refresh operation can be inserted between the access operations. That is, in the semiconductor memory in which refresh operations are performed automatically, it is possible to evaluate the minimum interval of supplying access requests. As a result, the evaluation time can be reduced with a reduction in the development period of the semiconductor memory.

Abstract: Embodiments of the invention provide an information recording device that can control the timing of information recording on a patterned medium, with a simplified configuration, and a control method for the information recording device. In one embodiment, an information recording device is provided which has a read/write head opposed to a patterned medium and moving in a relative form with respect to the patterned medium and is used to record information on the patterned medium. In accordance with a signal that the read/write head reads out from the patterned medium, a clock signal generator generates a clock signal pertaining to the timing in which the read/write head moves above the recording regions of the patterned medium, and information is recorded on the patterned medium in accordance with the information recording timing of the read/write head that has been determined in the relationship with the above-generated clock signal.

Abstract: A method for controlling a semiconductor memory in which a mode register can be set in a burst mode. To set an operation mode in the burst mode, the semiconductor memory is changed first from the burst mode, through a power-down mode, to a standby mode of non-burst mode. Then the semiconductor memory is changed to a mode register set mode to set the mode register when commands are input in the same predetermined sequence that is used in the non-burst mode.

Abstract: A semiconductor circuit which includes one or plural fuse circuits being disconnectable and having a connected or disconnected state and a control circuit controlling a controlled circuit is provided. The control circuit controls the controlled circuit according to the state of the fuse circuit or the states of the fuse circuits when a normal mode is designated and controls the controlled circuit according to the state of the fuse circuit or the states of the fuse circuits and an input signal or input signals when a test mode is designated.

Abstract: A data transfer method and system are provided that prevent the length of a time required for writing to a flash memory from appearing on the surface as a system operation when the flash memory is used in place of an SRAM. The method of transferring data includes the steps of writing data from a controller to a volatile memory, placing the volatile memory in a transfer state, transferring the data from the volatile memory in the transfer state to a nonvolatile memory, and releasing the volatile memory from the transfer state in response to confirming completion of the transfer of the data.

Abstract: A method for controlling a semiconductor memory in which mode register can be set in burst mode. To set an operation mode in burst mode, the semiconductor memory is changed first from the burst mode, through power-down mode, to standby mode of non-burst mode. Then the semiconductor memory is changed to mode register set mode to set the mode register when commands are input in the same predetermined sequence that is used in the non-burst mode.

Abstract: A method for controlling a semiconductor memory in which mode register can be set in burst mode. To set an operation mode in burst mode, the semiconductor memory is changed first from the burst mode, through power-down mode, to standby mode of non-burst mode. Then the semiconductor memory is changed to mode register set mode to set the mode register when commands are input in the same predetermined sequence that is used in the non-burst mode.

Abstract: A semiconductor memory includes a refresh timer and an arbiter for determining the order of precedence between an access operation and a refresh operation, in order to automatically perform refresh operations inside the memory. A detecting circuit operates in a test mode and outputs a detection signal indicating that the refresh operation is yet to be performed, when a new internal refresh request occurs before the refresh operation is performed. For example, the detection signal is output when the interval of access requests is short and no refresh operation can be inserted between the access operations. That is, in the semiconductor memory in which refresh operations are performed automatically, it is possible to evaluate the minimum interval of supplying access requests. As a result, the evaluation time can be reduced with a reduction in the development period of the semiconductor memory.

Abstract: A power supply circuit includes a first NMOS-type current mirror circuit which compares a first potential with a second potential, a second NMOS-type current mirror circuit which compares the first potential with a third potential, and a potential setting circuit which adjusts the first potential in response to outputs of the first and second NMOS-type current mirror circuits, such that the first potential falls between the second potential and the third potential.

Abstract: A method for controlling a semiconductor memory in which mode register can be set in burst mode. To set an operation mode in burst mode, the semiconductor memory is changed first from the burst mode, through power-down mode, to standby mode of non-burst mode. Then the semiconductor memory is changed to mode register set mode to set the mode register when commands are input in the same predetermined sequence that is used in the non-burst mode.

Abstract: A recording and reproducing separation type magnetic head has a recording head with an upper core and a lower core that writes information on a magnetic disk and a reproducing head with an upper magnetic film and a lower magnetic film, as sealed layers, that reads the information from the magnetic disk. A thickness of the upper part of the upper core is less than a thickness of the tip minute of the upper core. The magnetic head has excellent overwriting performance and achieves high speed transfer.

Abstract: A power supply circuit includes a first NMOS-type current mirror circuit which compares a first potential with a second potential, a second NMOS-type current mirror circuit which compares the first potential with a third potential, and a potential setting circuit which adjusts the first potential in response to outputs of the first and second NMOS-type current mirror circuits, such that the first potential falls between the second potential and the third potential.

Abstract: A recording and reproducing separation type magnetic head has a recording head with an upper core and a lower core that writes information on a magnetic disk and a reproducing head with an upper magnetic film and a lower magnetic film, as sealed layers, that reads the information from the magnetic disk. A thickness of the upper part of the upper core is less than a thickness of the tip minute of the upper core. The magnetic head has excellent overwriting performance and achieves high speed transfer.

Abstract: The artificial moving bed of this invention includes a fluid distribution apparatus consisting of an upper fluid distributor and a lower fluid distributor, and a plurality of processing chambers held and fixed between the upper and lower fluid distributors. Each fluid distributor has a rotary valve held in a slidable condition between a fixed supply valve and a pipe fixing plate. These fluid distributors are formed with fluid passages therein. The processing chambers are divided into several groups, each assigned a specific process. Using this artificial moving bed, the processing chambers are operated simultaneously and when the process is finished in each group of processing chambers, the fluid distribution apparatus is rotated clockwise when viewed from above so that each group of chambers proceeds to the next process, thus allowing continuous adsorption operation.