Abstract: A wiring substrate in which a capacitor is provided, the capacitor comprising a capacitor body including a plurality of dielectric layers and internal electrode layers provided between the different dielectric layers, wherein said capacitor body has, in at least one side face of said capacitor body, recesses extending in a thickness direction of said capacitor body from at least one of a first principal face of said capacitor body and a second principal face positioned on the side opposite to the first principal face.

Abstract: A wiring substrate in which a capacitor is provided, the capacitor comprising a capacitor body including a plurality of dielectric layers and internal electrode layers provided between the different dielectric layers, wherein said capacitor body has, in at least one side face of said capacitor body, recesses extending in a thickness direction of said capacitor body from at least one of a first principal face of said capacitor body and a second principal face positioned on the side opposite to the first principal face.

Abstract: An information processing system may include at least an image processing device and includes a receiving unit, a specifying unit, an acquiring unit, and an adjusting unit. The receiving unit receives a print request and identification information. The specifying unit specifies a queue corresponding to image forming device based on the identification information. The acquiring unit acquires the number of jobs stored in the specified queue. The adjusting unit adjusts the number of print services depending on whether the number of acquired jobs is equal to or larger than a predetermined value for the number of jobs set in the identification information and depending on whether the number of print services that process the jobs stored in the queue is equal to or smaller than a predetermined value for the number of print services set in the identification information.

Abstract: A print relay system capable of connecting to an image forming apparatus and a print service system, which is provided by a vendor that publishes a unique specification for executing data communication with the image forming apparatus includes an acquisition unit configured to, in response to the print service system receiving a printing instruction input by a user via a client, acquire data from the print service system according to a first specification, which is the unique specification for data communication between the print service system and a relay virtual printer, and a transmission unit configured to transmit the data acquired by the acquisition unit from the relay virtual printer to the image forming apparatus according to a second specification for executing data communication between the relay virtual printer and the image forming apparatus.

Abstract: A print relay system includes a receiving unit configured to receive, from an image forming apparatus, a request for registering information about the image forming apparatus to a print service, a generation unit configured to, in response to the receiving unit receiving the request, generate a relay virtual printer corresponding to the image forming apparatus that has transmitted the request, and a request unit configured to request the print service to register identification information for identifying the relay virtual printer.

Abstract: A capacitor is provided having a tough surface portion which prevents cracking that tends to occur when the capacitor is built-in or surface-mounted on a wiring board. A ceramic sintered body of the capacitor includes a capacitor forming layer portion, a cover layer portion and an interlayer portion. The capacitor forming layer portion has a laminated structure wherein ceramic dielectric layers and inner electrodes connected to a peripheral portion of capacitor via conductors, are alternately laminated. The cover layer portion is exposed at a surface portion of the ceramic body and has a laminated structure wherein ceramic dielectric layers and dummy electrodes not connected to the capacitor via conductors, are alternately laminated.

Abstract: A capacitor comprising: a capacitor body including a plurality of laminated dielectric layers, a plurality of inner electrode layers which are respectively disposed between mutually adjacent ones of the dielectric layers, a first main surface located in a laminated direction of the dielectric layers, and a second main surface opposite to the first main surface; a first outer electrode formed on the first main surface of the capacitor body and electrically connected to the inner electrode layers; a second outer electrode formed on the second main surface of the capacitor body and electrically connected to the inner electrode layers; a first dummy electrode formed on the first main surface of the capacitor body; and a second dummy electrode formed on the second main surface of the capacitor body.

Abstract: A method for manufacturing a wiring board with built-in component. The method provides a secure connection between a component and interlayer insulating layers so that the wiring board with built-in component has excellent reliability. The wiring board is manufactured through a core board preparation step, a component preparation step, an accommodation step and a height alignment step. In the core board preparation step, a core board having an accommodation hole therein is prepared. In the component preparation step, a ceramic capacitor having therein a plurality of protruding conductors which protrudes from a capacitor rear surface is prepared. In the accommodation step, the ceramic capacitor is accommodated in the accommodation hole with the core rear surface facing the same side as the capacitor rear surface. In the height alignment step, a surface of a top portion of the protruding conductor and a surface of a conductor layer formed on the core rear surface are aligned to the same height.

Abstract: A capacitor comprising: a capacitor body including a plurality of laminated dielectric layers, a plurality of inner electrode layers which are respectively disposed between mutually adjacent ones of the dielectric layers, a first main surface located in a laminated direction of the dielectric layers, and a second main surface opposite to the first main surface; a first outer electrode formed on the first main surface of the capacitor body and electrically connected to the inner electrode layers; a second outer electrode formed on the second main surface of the capacitor body and electrically connected to the inner electrode layers; a first dummy electrode formed on the first main surface of the capacitor body; and a second dummy electrode formed on the second main surface of the capacitor body.

Abstract: A wiring substrate in which a capacitor is provided, the capacitor comprising a capacitor body including a plurality of dielectric layers and internal electrode layers provided between the different dielectric layers, wherein said capacitor body has, in at least one side face of said capacitor body, recesses extending in a thickness direction of said capacitor body from at least one of a first principal face of said capacitor body and a second principal face positioned on the side opposite to the first principal face.

Abstract: A wiring substrate in which a capacitor is provided, the capacitor comprising a capacitor body including a plurality of dielectric layers and internal electrode layers provided between the different dielectric layers, wherein said capacitor body has, in at least one side face of said capacitor body, recesses extending in a thickness direction of said capacitor body from at least one of a first principal face of said capacitor body and a second principal face positioned on the side opposite to the first principal face.

Abstract: A wiring substrate in which a capacitor is provided, the capacitor comprising a capacitor body including a plurality of dielectric layers and internal electrode layers provided between the different dielectric layers, wherein said capacitor body has, in at least one side face of said capacitor body, recesses extending in a thickness direction of said capacitor body from at least one of a first principal face of said capacitor body and a second principal face positioned on the side opposite to the first principal face.

Abstract: A ceramic capacitor includes a capacitor body and a metal layer arranged on an outer surface of the capacitor body. The outer surface includes: a first capacitor major surface; a second capacitor major surface opposite to the first capacitor major surface in a thickness direction of the capacitor body; and a capacitor lateral surface between the first and second capacitor major surfaces. The capacitor body includes a first layer section and a second layer section. The first layer section includes a plurality of ceramic dielectric layers and a plurality of internal electrodes, wherein the ceramic dielectric layers and the internal electrodes are layered alternately. The second layer section is exposed at the first capacitor major surface, and includes a corner portion at a boundary between the first capacitor major surface and the capacitor lateral surface. The metal layer covers the corner portion of the second layer section.

Abstract: A method for manufacturing a ceramic capacitor embedded in a wiring substrate, the ceramic capacitor including a capacitor body which has a pair of capacitor main surfaces and a plurality of capacitor side surfaces also has a structure in which a plurality of internal electrodes are alternately layered through a ceramic dielectric layer, the method has (a) laminating ceramic-made green sheets and combining the green sheets into one, to form a multi-device-forming multilayer unit in which a plurality of product areas, each of which becomes the ceramic capacitor, are arranged in longitudinal and lateral directions along a plane direction, (b) forming a groove portion to form a chamfer portion at a boundary portion between at least one of the capacitor main surfaces and the plurality of capacitor side surfaces, (c) sintering the multi-device-forming multilayer unit, and (d) dividing the product areas into each product area along the groove portion.

Abstract: A dielectric structure including a metal foil, a dielectric layer and a conductor layer provided in this order, wherein the metal foil has a thickness of from 10 to 40 ?m, the dielectric layer has a thickness of from 0.3 to 5 ?m, and the conductor layer has a thickness of from 0.3 to 10 ?m. The dielectric structure has plural vias which are separated from each other, and which penetrate through both of the dielectric layer and the conductor layer. The vias of the dielectric layer have different diameters which are in a range of from 100 to 300 ?m, a diameter of each of the vias of the conductor layer is larger than a diameter of a corresponding via of the dielectric layer by 5 to 50 ?m, and a minimum via pitch is from 100 to 350 ?m.

Abstract: A dielectric structure including a metal foil, a dielectric layer and a conductor layer provided in this order, wherein the metal foil has a thickness of from 10 to 40 ?m, the dielectric layer has a thickness of from 0.3 to 5 ?m, and the conductor layer has a thickness of from 0.3 to 10 ?m. The dielectric structure has plural vias which are separated from each other, and which penetrate through both of the dielectric layer and the conductor layer. The vias of the dielectric layer have different diameters which are in a range of from 100 to 300 ?m, a diameter of each of the vias of the conductor layer is larger than a diameter of a corresponding via of the dielectric layer by 5 to 50 ?m, and a minimum via pitch is from 100 to 350 ?m.

Abstract: A via array capacitor including a capacitor body having a first main surface and a second main surface and having a structure in which dielectric layers and inner electrode layers are alternately laminated; a plurality of via conductors which conduct the inner electrode layers to each other and are, as a whole, arranged in array form; and metal-containing layers which are disposed on at least one of the first main surface and the second main surface, wherein a total volume of the inner electrode layers and the metal-containing layers included in the via array capacitor is from 45 vol.% to 95 vol.% of a volume of the via array capacitor.