Abstract: A multi-layer capacitor including a capacitor body including dielectric layers, and first and second internal electrode layers which are alternately laminated by mediation of the dielectric layers. The laminate of the first and second internal electrode layers and the dielectric layers are co-fired. The capacitor body further includes first and second electrode terminals formed on one main surface of the capacitor body. At least a single first via electrode extends through the capacitor body in the lamination direction of the capacitor body so as to connect the first electrode terminal and the first internal electrode layers, and at least a single second via electrode extends through the capacitor body in the lamination direction of the capacitor body so as to connect the second electrode terminal and the second internal electrode layers. The via electrodes have an aspect ratio of 4 to 30 as measured after firing.

Abstract: A multilayer ceramic capacitor (10) having reduced inductance which is separated into a first layer body (11) and a second layer body (12). The first layer body (11) and the second layer body (12) are formed by alternately layering inner electrodes (inner electrode 13a, inner electrode 13b) so as to face each other and sandwich ceramic layers (14). The ceramic layers (14) of the second layer body (12) are thicker than the ceramic layers (14) of the first layer body (11), so as to compensate for electrode height difference. Moreover, in the second layer body (12), the inner electrodes (13b) are electrically connected by via electrode (15b) so that the part of the via electrode (15b) extending without connection to an inner electrode (13b) is shortened.

Abstract: A laminated ceramic capacitor 10 divided into a first laminate 11, a second laminate 12, a third laminate 13, and a fourth laminate 14. The first laminate 11 includes a ceramic layer 15 serving as a dielectric layer. The ceramic layer 15 is thicker than a ceramic layer 17 sandwiched between internal electrodes 16a in the second laminate 12 or the fourth laminate 14, and thinner than 20 times the thickness of the ceramic layer 17. The third laminate 13 includes dielectric layers, which serve as the ceramic layers 17, and has a thickness of 5% of the total thickness of the second laminate 12 and the fourth laminate 14. Accordingly, the third laminate 13 achieves the function of absorbing an electrode-induced thickness differential. Also, by means of regulating the thickness of the first laminate 11, portions of via electrodes 18 that extend without being electrically connected to the internal electrodes 16b can be shortened.

Abstract: A capacitor comprising: a thin film laminate including a plurality of dielectric thin films and a plurality of electrode conductor thin films laminated alternately; and first kind terminals and second kind terminals formed over a first main surface of said thin film laminate and isolated from each other in a DC current, wherein a first kind electrode conductor thin films electrically connecting with said first kind terminals and a second kind electrode conductor thin films electrically connecting with said second kind terminals are so alternately laminated in a laminate direction as are separated by said dielectric thin films, and a first dielectric thin film, an other kind electrode conductor thin film and a second dielectric thin film are laminated in this order between one same kind electrode conductor thin film and other same kind electrode conductor thin film adjoining in said laminate direction, and first through holes, second through holes and the like are defined herein.

Abstract: A first ceramic substrate includes a substrate (2) and a glaze layer (3), wherein the glaze layer has a surface having an Ra of 0.02 ?m or less and a Ry of 0.25 ?m or less. A second ceramic substrate is formed by subjecting a glass layer (24) formed on a surface of a substrate (2) to heating-and-pressurizing treatment, thereby forming a glaze layer (3) on the substrate (2), and planarization-polishing the surface of the glaze layer. A third ceramic substrate includes a substrate (2), a glaze layer (3) containing substantially no pores formed on the substrate (2) and the surface thereof being planarization-polished, and a wiring pattern (21), wherein at least one first end of the wiring pattern is exposed to the glaze layer (3) surface of the substrate (1), and at least one second end is exposed to another surface of the substrate (1).

Abstract: A ceramic substrate for a thin film electronic component, a production method thereof, and a thin film electronic component using the ceramic substrate A first substrate (1) includes a dense glass-ceramic mixed layer (33) containing glass in its surface portion. A second substrate is prepared such that a glass layer (32) formed on a surface of a substrate base portion (2) is subjected to a heat-pressure treatment so as to form or rather partly change the glass portion (32) into a dense glass-ceramic mixed layer (33) in which glass is dispersed into a surface portion of the substrate base portion (2). A surface of the dense glass-ceramic mixed layer (33) is then subjected to grinding or rather polishing to flatten and expose a surface of the dense glass-ceramic mixed layer (32). A third substrate includes a substrate base portion (2) having a dense glass-ceramic mixed layer (33) containing glass on a surface portion in one face side, and a wiring pattern (21) formed inside the substrate base portion (2).

Abstract: A method for producing a ceramic substrate which employs a cofiring process using restraint sheets in which a second ceramic green sheet 7 is laminated on a green ceramic substrate 30 so as to cover surface conductors 32 of the green ceramic substrate 30, the second ceramic green sheet 7 subsequently being integrated with the green ceramic substrate 30. Restraint sheets 9, which are not sintered at a sintering temperature at which the green ceramic substrate 30 is sintered, are laminated on corresponding opposite sides of the green ceramic substrate 30 so as to restrain the green ceramic substrate 30 together with the second ceramic green sheet 7. The second ceramic green sheet 7 and the green ceramic substrate 30 are fired at a temperature at which the second ceramic green sheet 7 and the green ceramic substrate 30 are integrally sintered, whereas the restraint sheets 9 are not sintered, to thereby yield a ceramic substrate 40.

Abstract: A dielectric porcelain composition comprising Ba, Nd, Pr, Bi, Ti and at least one of Na and K and satisfying a condition that when the composition is expressed by composition formula: BaO—aNdO3/2—bPrO11/6—cBiO3/2—dTiO2—eAO1/2, wherein A is at least one of Na and K, and a, b, c, d and e represent a molar ratio, a, b, c, d and e are in respective ranges of 1.5?a?2.6, 0.02?b?1.00, 0.2?c?0.6, 4.5?d?5.5 and 0.02?e?0.30.

Abstract: A multi-layer capacitor including a capacitor body including dielectric layers, and first and second internal electrode layers which are alternately laminated by mediation of the dielectric layers. The laminate of the first and second internal electrode layers and the dielectric layers are co-fired. The capacitor body further includes first and second electrode terminals formed on one main surface of the capacitor body. At least a single first via electrode extends through the capacitor body in the lamination direction of the capacitor body so as to connect the first electrode terminal and the first internal electrode layers, and at least a single second via electrode extends through the capacitor body in the lamination direction of the capacitor body so as to connect the second electrode terminal and the second internal electrode layers. The via electrodes have an aspect ratio of 4 to 30 as measured after firing.

Abstract: A capacitor comprising: a thin film laminate including a plurality of dielectric thin films and a plurality of electrode conductor thin films laminated alternately; and first kind terminals and second kind terminals formed over a first main surface of said thin film laminate and isolated from each other in a DC current, wherein a first kind electrode conductor thin films electrically connecting with said first kind terminals and a second kind electrode conductor thin films electrically connecting with said second kind terminals are so alternately laminated in a laminate direction as are separated by said dielectric thin films, and a first dielectric thin film, an other kind electrode conductor thin film and a second dielectric thin film are laminated in this order between one same kind electrode conductor thin film and other same kind electrode conductor thin film adjoining in said laminate direction, and first through holes, second through holes and the like are defined herein.

Abstract: A capacitor includes a capacitor main body having a front surface on which a semiconductor device is to be mounted and a rear surface at which the capacitor main body is to be mounted on a first main surface of a circuit substrate, a plurality of internal electrodes disposed within the capacitor main body, and a plurality of via conductors penetrating the capacitor main body between the front surface and the rear surface and electrically connected to the internal electrodes, wherein the capacitor main body has a first dielectric layer located on a side of the capacitor main body closer to the front surface and a second dielectric layer located on a side of the first dielectric layer closer to the rear surface, the second dielectric layer having a higher thermal expansion coefficient and a higher dielectric constant than the first dielectric layer.

Abstract: A method for producing a multi-layer ceramic capacitor 10 in which reliability of electrical contact between a via electrode 28 and an internal electrode layer 24 (24a or 24b) provided between ceramic layers 22 is enhanced. A laminated sheet 100 including ceramic layers 22 and internal electrode layers 24, the layers 22 and 24 being alternately laminated and combined together, is formed, through-holes 26 are formed in the laminated sheet 100 by means of laser irradiation, and an electrically conductive material is charged into the through-holes 26 using charging container 110, to thereby form via electrodes 28. The electrically conductive material is charged, under application of pressure, into each of the through-holes 26 via an opening of the through-hole 26.

Abstract: An assembly includes a semiconductor device having surface-connecting terminals, a substrate having surface-connecting pads, and a capacitor having an approximately plate-shaped capacitor main body having a first surface on which the semiconductor device is mounted and a second surface at which the capacitor main body is mounted on the substrate and a plurality of electrically conductive vias penetrating the capacitor main body between the first and second surfaces and connected to the surface-connecting terminals and the surface-connecting pads.

Abstract: A multi-layer capacitor including a capacitor body including dielectric layers, and first and second internal electrode layers which are alternately laminated by mediation of the dielectric layers. The laminate of the first and second internal electrode layers and the dielectric layers are co-fired. The capacitor body further includes first and second electrode terminals formed on one main surface of the capacitor body. At least a single first via electrode extends through the capacitor body in the lamination direction of the capacitor body so as to connect the first electrode terminal and the first internal electrode layers, and at least a single second via electrode extends through the capacitor body in the lamination direction of the capacitor body so as to connect the second electrode terminal and the second internal electrode layers. The via electrodes have an aspect ratio of 4 to 30 as measured after firing.

Abstract: A multi-layer capacitor including a capacitor body including dielectric layers, and first and second internal electrode layers which are alternately laminated by mediation of the dielectric layers. The laminate of the first and second internal electrode layers and the dielectric layers are co-fired. The capacitor body further includes first and second electrode terminals formed on one main surface of the capacitor body. At least a single first via electrode extends through the capacitor body in the lamination direction of the capacitor body so as to connect the first electrode terminal and the first internal electrode layers, and at least a single second via electrode extends through the capacitor body in the lamination direction of the capacitor body so as to connect the second electrode terminal and the second internal electrode layers. The via electrodes have an aspect ratio of 4 to 30 as measured after firing.

Abstract: A dielectric composition is based on a BaO—MgO—Nb2O5 system material (BMN system material) having a dielectric constant, &egr;, of about 30, a large Q-value (no-load quality coefficient) and a comparatively small absolute value of the temperature coefficient (&tgr;f) of its resonance frequency but containing no expensive Ta. The dielectric material has a composite perovskite crystal structure as the main crystal phase, wherein a predetermined amount of KNbO3 is added to a BMN system material. The high frequency characteristics can be further improved by partially replacing Nb with Sb and partially replacing the B site of the perovskite crystal structure with Sn.

Abstract: A dielectric composition is based on a BaO—MgO—Nb2O5 system material (BMN system material) having a dielectric constant, &egr;, of about 30, a large Q-value (no-load quality coefficient) and a comparatively small absolute value of the temperature coefficient (&tgr;f) of its resonance frequency but containing no expensive Ta. The dielectric material has a composite perovskite crystal structure as the main crystal phase, wherein a predetermined amount of KNbO3 is added to a BMN system material. The high frequency characteristics can be further improved by partially replacing Nb with Sb and partially replacing the B site of the perovskite crystal structure with Sn.

Abstract: A dielectric porcelain composition comprising Ba, Nd, Pr, Bi, Ti and at least one of Na and K and satisfying a condition that when the composition is expressed by composition formula: BaO-aNdO3/2-bPrO11/6-cBiO3/2-dTiO2-eAO1/2, wherein A is at least one of Na and K, and a, b, c, d and e represent a molar ratio, a, b, c, d and e are in respective ranges of 1.5≦a≦2.6, 0.02≦b≦1.00, 0.2≦c≦0.6, 4.5≦d≦5.5 and 0.02≦e≦0.30.

Abstract: A cylinder head structure for an engine, including grooves (18; 12a) in a top surface (2; 2a) of a cylinder head body (1; 1a) such that they surround an associated a fuel injection nozzle hole (11; 8a). Valve tappet guide holes (6; 3a) are also formed in the top surface (2; 2a) of the cylinder head body (1; 1a) around each of the fuel injection nozzle holes (11; 8a). The grooves (18; 12a) connect the adjacent tappet guide holes (6; 3a) and surround the associated nozzle or spark plug hole. Cylinder head bolt holes (15; 9a) are also formed around the tappet guide holes (6; 3a). When cylinder head bolts are tightened to join the cylinder head with a cylinder block, a radiant tension (F) is generated from the cylinder head bolt heads which are in contact with the cylinder head top surface. This radiant tension would cause cracking around the injection nozzle hole (11; 8a).