Patents by Inventor Jun Pin Tan
Jun Pin Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170221537Abstract: Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enabling high-speed FPGA boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated circuit devices are able to accommodate. In order to enable high-speed boot-up, dedicated address registers are implemented for each data line segment of a data line, which in turn significantly reduces configuration random access memory (CRAM) write time (e.g., by a factor of at least two).Type: ApplicationFiled: April 17, 2017Publication date: August 3, 2017Inventors: Jun Pin Tan, Kiun Kiet Jong, Lai Pheng Tan
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Patent number: 9627019Abstract: Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enabling high-speed FPGA boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated circuit devices are able to accommodate. In order to enable high-speed boot-up, dedicated address registers are implemented for each data line segment of a data line, which in turn significantly reduces configuration random access memory (CRAM) write time (e.g., by a factor of at least two).Type: GrantFiled: June 29, 2016Date of Patent: April 18, 2017Assignee: Altera CorporationInventors: Jun Pin Tan, Kiun Kiet Jong, Lai Pheng Tan
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Publication number: 20160307612Abstract: Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enabling high-speed FPGA boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated circuit devices are able to accommodate. In order to enable high-speed boot-up, dedicated address registers are implemented for each data line segment of a data line, which in turn significantly reduces configuration random access memory (CRAM) write time (e.g., by a factor of at least two).Type: ApplicationFiled: June 29, 2016Publication date: October 20, 2016Inventors: Jun Pin Tan, Kiun Kiet Jong, Lai Pheng Tan
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Patent number: 9401190Abstract: Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enabling high-speed FPGA boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated circuit devices are able to accommodate. In order to enable high-speed boot-up, dedicated address registers are implemented for each data line segment of a data line, which in turn significantly reduces configuration random access memory (CRAM) write time (e.g., by a factor of at least two).Type: GrantFiled: April 13, 2015Date of Patent: July 26, 2016Assignee: Altera CorporationInventors: Jun Pin Tan, Kiun Kiet Jong, Lai Pheng Tan
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Patent number: 9383802Abstract: A method of operating an integrated circuit that includes a plurality of registers may include receiving a sleep mode request for the integrated circuit. The sleep mode request may be a control signal received with control circuitry on the integrated circuit. The plurality of registers may be configured to operate as a scan chain when the sleep mode request is received. Integrated circuit state information that are stored in the plurality of registers may be retrieved by operating the scan chain and stored in a memory module. The integrated circuit may be placed in a sleep mode. Placing the integrated circuit in the sleep mode may reduce power consumption of the integrated circuit.Type: GrantFiled: June 20, 2013Date of Patent: July 5, 2016Assignee: Altera CorporationInventors: Jun Pin Tan, Kiun Kiet Jong
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Patent number: 8941408Abstract: Techniques and mechanisms dynamically configure shift registers among registers composing data registers in a circuit such as a Programmable Logic Device (PLD). A configuration bit stream used to configure the PLD may have a reduced size if “phantom bits” not corresponding to configuration elements are removed. Shift registers may be dynamically configured such that registers which do not correspond to physical configuration elements may be skipped. Thus, a PLD may be programmed with a configuration bit stream without phantom bits.Type: GrantFiled: February 28, 2013Date of Patent: January 27, 2015Assignee: Altera CorporationInventors: Jun Pin Tan, Kiun Kiet Jong
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Publication number: 20140240000Abstract: Techniques and mechanisms dynamically configure shift registers among registers composing data registers in a circuit such as a Programmable Logic Device (PLD). A configuration bit stream used to configure the PLD may have a reduced size if “phantom bits” not corresponding to configuration elements are removed. Shift registers may be dynamically configured such that registers which do not correspond to physical configuration elements may be skipped. Thus, a PLD may be programmed with a configuration bit stream without phantom bits.Type: ApplicationFiled: February 28, 2013Publication date: August 28, 2014Inventors: Jun Pin Tan, Kiun Kiet Jong
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Patent number: 8629689Abstract: An integrated circuit (IC) includes a circuit, an encoder, and a decoder. The circuit is coupled to circuitry in the IC via a first set of interconnect fabricated using a metal layer. The encoder encodes a plurality of address lines to provide a plurality of encoded address lines. The decoder decodes the plurality of address lines. The plurality of encoded address lines are routed using a second set of interconnect fabricated using the metal layer.Type: GrantFiled: May 18, 2012Date of Patent: January 14, 2014Assignee: Altera CorporationInventors: Jun Pin Tan, Kiun Kiet Jong
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Patent number: 8612814Abstract: Integrated circuits with error detection circuitry are provided. Integrated circuits may include memory cells organized into frames. The error detection circuitry may compress each frame to scan for soft errors. The error detection circuitry may include multiple input shift registers (MISRs), a data register, and a signature comparator. The data frames may be read, compressed, and shifted into the MISRs in parallel. After all the data frames have been read, the MISRs may provide a scanned MISR signature at their outputs. Computer-aided design (CAD) tools may be used to calculate a precomputed MISR signature. The precomputed MISR signature may be loaded into the data register. The signature comparator compares the scanned MISR signature with the precomputed MISR signature. If the signatures match, then the device is free of soft errors. If the signatures do not match, then at least one soft error exists.Type: GrantFiled: June 14, 2010Date of Patent: December 17, 2013Assignee: Altera CorporationInventors: Jun Pin Tan, Kiun Kiet Jong, Boon Jin Ang
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Patent number: 8437200Abstract: Methods and circuits for zeroization verification of the memory in an integrated circuit (IC) are provided. One method includes sequentially reading frames from a block of the memory, and sequentially performing a logical operation between each of the frames and the content of a signature register. The result of the logical operation is stored back in the signature register. In another operation, a hardware logical comparison is made between a device hardwired signature block and the content of the signature register, after the logical operations for all the frames have been performed. The device hardwired signature block is a hardware implemented constant that is unavailable for loading in registers of the IC. The block of the memory is verified to hold a fixed value when the result of the hardware logical comparison indicates that the device hardwired signature block is equal to the content of the signature register.Type: GrantFiled: February 7, 2011Date of Patent: May 7, 2013Assignee: Altera CorporationInventors: Jun Pin Tan, Kiun Kiet Jong
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Patent number: 8327199Abstract: Integrated circuits (ICs) with configurable test pins and a method of testing an IC are disclosed. An IC has input/output (I/O) pins that can be configured either as a test input pin, a test output pin or a user I/O pin. Selector circuits are used to selectively route and couple the I/O pins to various logic blocks and test circuitry on the IC. Selector circuits are also used to selectively couple either a user output or a test output to different I/O pins on the IC. Switches are used to configure the selector circuits and route test signals within the IC. Different configurations of the switches determine how the signals are routed. Test input signals from an I/O pin may be routed to any test circuitry within the IC and test output signals from a test circuit may be routed to any I/O pin on the IC.Type: GrantFiled: March 5, 2010Date of Patent: December 4, 2012Assignee: Altera CorporationInventors: Jayabrata Ghosh Dastidar, Chiew Khiang Kuit, Siew Ling Yeoh, Jun Pin Tan, Kok Sun Chia, Yee Liang Tan, Kar Keng Chua
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Patent number: 8189362Abstract: Techniques for encoding and decoding fuse data to reduce sense current are disclosed. An embodiment to encode fuse sense data includes inverting each of the bits of the fuse data and using an individual fuse as a flag bit to record the data inversion. The states of the respective fuses may represent different logic states. A fuse may be blown to indicate a logic one and likewise, an unblown fuse may indicate a logic zero. A blown fuse and an unblown fuse may have different current consumption. An unblown fuse may consume more sensing current compared to a blown fuse. Another embodiment to decode the encoded fuse data includes embedded logic circuits and a separate fuse as a flag bit. Encoding and decoding fuse data may reduce fuse sensing current.Type: GrantFiled: June 1, 2011Date of Patent: May 29, 2012Assignee: Altera CorporationInventors: Jun Pin Tan, Tze Swan Tan, Chuan Khye Chai, Boon Jin Ang, Kar Keng Chua
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Publication number: 20110292711Abstract: Techniques for encoding and decoding fuse data to reduce sense current are disclosed. An embodiment to encode fuse sense data includes inverting each of the bits of the fuse data and using an individual fuse as a flag bit to record the data inversion. The states of the respective fuses may represent different logic states. A fuse may be blown to indicate a logic one and likewise, an unblown fuse may indicate a logic zero. A blown fuse and an unblown fuse may have different current consumption. An unblown fuse may consume more sensing current compared to a blown fuse. Another embodiment to decode the encoded fuse data includes embedded logic circuits and a separate fuse as a flag bit. Encoding and decoding fuse data may reduce fuse sensing current.Type: ApplicationFiled: June 1, 2011Publication date: December 1, 2011Inventors: Jun Pin Tan, Tze Swan Tan, Chuan Khye Chai, Boon Jin Ang, Kar Keng Chua
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Patent number: 7978493Abstract: Techniques for encoding and decoding fuse data to reduce sense current are disclosed. An embodiment to encode fuse sense data includes inverting each of the bits of the fuse data and using an individual fuse as a flag bit to record the data inversion. The states of the respective fuses may represent different logic states. A fuse may be blown to indicate a logic one and likewise, an unblown fuse may indicate a logic zero. A blown fuse and an unblown fuse may have different current consumption. An unblown fuse may consume more sensing current compared to a blown fuse. Another embodiment to decode the encoded fuse data includes embedded logic circuits and a separate fuse as a flag bit. Encoding and decoding fuse data may reduce fuse sensing current.Type: GrantFiled: September 18, 2008Date of Patent: July 12, 2011Assignee: Altera CorporationInventors: Jun Pin Tan, Tze Swan Tan, Chuan Khye Chai, Boon Jin Ang, Kar Keng Chua
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Patent number: 7787314Abstract: In mask programmable integrated circuit, such as a structured ASIC, a delay chain provides a delay that is set by a mask programmable switch. The delay chain receives an input to allow the delay mask programmed delay to be overridden using a JTAG controller. This allows testing of different delays. The input may also be provided by a fuse block, so that the fuse block can override the mask programmable switch, thus allowing a delay to be changes after mask programming.Type: GrantFiled: September 11, 2008Date of Patent: August 31, 2010Assignee: Altera CorporationInventors: Jun Pin Tan, Wei Yee Koay, Boon Jin Ang, Choong Kit Wong, Guang Sheng Soh
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Publication number: 20100061166Abstract: In mask programmable integrated circuit, such as a structured ASIC, a delay chain provides a delay that is set by a mask programmable switch. The delay chain receives an input to allow the delay mask programmed delay to be overridden using a JTAG controller. This allows testing of different delays. The input may also be provided by a fuse block, so that the fuse block can override the mask programmable switch, thus allowing a delay to be changes after mask programming.Type: ApplicationFiled: September 11, 2008Publication date: March 11, 2010Applicant: ALTERA CORPORATIONInventors: Jun Pin Tan, Wei Yee Koay, Boon Jin Ang, Choong Kit Wong, Guang Sheng Soh
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Patent number: 7565390Abstract: In circuitry such as a programmable logic device (“PLD”), each of several multiplier blocks includes partial products generation circuitry and partial products addition circuitry. Two such multiplier blocks can be used together to provide multiply-accumulate (“MAC”) capability. The partial products addition circuitry in one of the paired blocks is used to add each successive product produced by the other paired block to a previous accumulation of products in the first-mentioned paired block. Provisions are also made for accumulating any overflow from operation of the partial products addition circuitry in the first-mentioned paired block.Type: GrantFiled: March 23, 2005Date of Patent: July 21, 2009Assignee: Altera CorporationInventors: Tat Mun Lui, Bee Yee Ng, Jun Pin Tan, Boon Jin Ang