Abstract: A source driver including a digital-to-analog converter and an output buffer with an interpolation function is disclosed. A digital-to-analog converter converts a plurality of digital input voltages into a plurality of analog input voltages. The output buffer interpolates the analog input voltages. The output buffer outputs a first interpolated output voltage at a first time and a second interpolated output voltage at a second time respectively. A first interpolated voltage output curve of the first interpolated output voltage versus a digital input code and a second interpolated voltage output curve of the second interpolated output voltage versus the digital input code are both non-linear and opposite each other. The output buffer averages the first interpolated voltage output curve at the first time and the second interpolated voltage output curve at the second time to achieve a linear interpolated voltage characteristic.

Abstract: A source driver module, a display device and a method for driving a display panel are provided. The method for driving a display panel is applicable to the source driver module, which includes a source driver circuit, a first switch coupled between the source driver circuit and a first end of a first data line, and a second switch coupled between the source driver circuit and a second end of the first data line. The method for driving the display panel includes: when the display panel displays a first image, the source driver circuit outputs a first voltage signal to the first end of the first data line through the first switch, and when the display panel displays a second image after displaying the first image, the source driver circuit outputs a second voltage signal to the second end of the first data line through the second switch.

Abstract: A source driver including a digital-to-analog converter and an output buffer with an interpolation function is disclosed. A digital-to-analog converter converts a plurality of digital input voltages into a plurality of analog input voltages. The output buffer interpolates the analog input voltages. The output buffer outputs a first interpolated output voltage at a first time and a second interpolated output voltage at a second time respectively. A first interpolated voltage output curve of the first interpolated output voltage versus a digital input code and a second interpolated voltage output curve of the second interpolated output voltage versus the digital input code are both non-linear and opposite each other. The output buffer averages the first interpolated voltage output curve at the first time and the second interpolated voltage output curve at the second time to achieve a linear interpolated voltage characteristic.

Abstract: A display apparatus including a voltage buffer, a display panel and a pixel loading compensation circuit is disclosed. The voltage buffer is used to receive a ramp voltage and output an output current. The display panel includes pixel switches and pixel capacitors. The pixel switches are arranged in parallel and coupled to the voltage buffer. The pixel capacitors are coupled between the pixel switches and ground. The pixel loading compensation circuit includes compensation switches and compensation current sources. The compensation switches corresponding to the pixel switches are arranged in parallel and coupled to the voltage buffer. The compensation current sources are coupled between the compensation switches and ground. The operation of the compensation switches is opposite to the operation of the corresponding pixel switches.

Abstract: A display driving method is disclosed. The display driving method includes the following steps: (A) generating a gate driving signal having a turn-on period by a gate driver; (B) generating a source driving signal by a source driver; the source driving signal has a first waveform corresponding to a first region and has a second waveform corresponding to a second region; (C) outputting, by a controller of a display device, a first control signal to allow the second waveform to be similar to the first waveform in the turn-on period.

Abstract: A display apparatus and a voltage calibration method are disclosed. The display apparatus includes a ramp voltage generator, a ramp counter and a timing controller. The ramp voltage generator is configured to generate a ramp voltage. The ramp counter is coupled to the ramp voltage generator and configured to start counting when the ramp voltage generator generates the ramp voltage. The timing controller is coupled to the ramp voltage generator and the ramp counter respectively. When the ramp voltage is increased to be equal to a reference voltage, the timing controller compares an instant count value of the ramp counter with a default value and selectively calibrates a rising slope of the ramp voltage generated by the ramp voltage generator according to a comparing result of the instant count value and the default value.

Abstract: The present invention provides a driving circuit, applied to an In-cell touch display panel. The In-cell touch display panel has a touch period and a data driving period. The touch period occurs between the data driving period corresponding to a first data line and another data driving period corresponding to a second data line. A common voltage (VCOM) voltage of the In-cell touch display panel has a first level and a second level. The driving circuit includes a determining module and a compensating module. The determining module determines whether a difference between the first level and the second level is larger than a preset value. The compensating module is coupled to the determining module. When the determining result is that the difference between the first level and the second level is larger than the preset value, the compensating module compensates the common voltage in the touch period, so that the first level and the second level are substantially equal.

Abstract: A display panel driving device is configured to drive a display panel. The display panel driving device includes a driving unit, a digital circuit unit and a selecting unit. The driving unit includes a first channel and a second channel. The first channel includes a first amplifier, and the second channel comprises a second amplifier. The digital circuit unit is coupled to the driving unit, and configured to output a first signal and a second signal to the first channel and the second channel respectively. The selecting unit is coupled to the driving unit. When the first signal and the second signal are the same, the selecting unit optionally switches off the first amplifier or the second amplifier.

Abstract: A display apparatus including a voltage buffer, a display panel and a pixel loading compensation circuit is disclosed. The voltage buffer is used to receive a ramp voltage and output an output current. The display panel includes pixel switches and pixel capacitors. The pixel switches are arranged in parallel and coupled to the voltage buffer. The pixel capacitors are coupled between the pixel switches and ground. The pixel loading compensation circuit includes compensation switches and compensation current sources. The compensation switches corresponding to the pixel switches are arranged in parallel and coupled to the voltage buffer. The compensation current sources are coupled between the compensation switches and ground. The operation of the compensation switches is opposite to the operation of the corresponding pixel switches.

Abstract: An amplifier circuit and a buffer amplifier are provided. The amplifier circuit includes an operational amplifier stage, an output stage, a first compensation capacitor, and a first decoupling circuit. The operational amplifier stage is coupled between a first input terminal, a second input terminal, a first control node, and a second control node. The first compensation capacitor is coupled between the output terminal and the first control node. The first decoupling circuit has a first switch, a first current source and a first ground terminal. The first switch is coupled to the first control node, and the first current source is connected between the first switch and the first ground terminal. The decoupling circuit is used for providing a discharging path for the first coupling current of the first compensation capacitor.

Abstract: A display apparatus and a voltage calibration method are disclosed. The display apparatus includes a ramp voltage generator, a ramp counter and a timing controller. The ramp voltage generator is configured to generate a ramp voltage. The ramp counter is coupled to the ramp voltage generator and configured to start counting when the ramp voltage generator generates the ramp voltage. The timing controller is coupled to the ramp voltage generator and the ramp counter respectively. When the ramp voltage is increased to be equal to a reference voltage, the timing controller compares an instant count value of the ramp counter with a default value and selectively calibrates a rising slope of the ramp voltage generated by the ramp voltage generator according to a comparing result of the instant count value and the default value.

Abstract: A source driver module, a display device and a method for driving a display panel are provided. The method for driving a display panel is applicable to the source driver module, which includes a source driver circuit, a first switch coupled between the source driver circuit and a first end of a first data line, and a second switch coupled between the source driver circuit and a second end of the first data line. The method for driving the display panel includes: when the display panel displays a first image, the source driver circuit outputs a first voltage signal to the first end of the first data line through the first switch, and when the display panel displays a second image after displaying the first image, the source driver circuit outputs a second voltage signal to the second end of the first data line through the second switch.

Abstract: A panel display position fine adjustment method is disclosed. The panel display position fine adjustment method includes steps of: (a) providing a fixed first synchronization timing signal; (b) generating a first control signal, a second control signal, and a third control signal according to the first synchronization timing signal, wherein the second control signal is turned on earlier than the first control signal and the third control signal is turned on later than the first control signal; (c) when the first display driver is controlled by the first control signal, the display area is not moved; (d) when the first display driver is controlled by the second control signal, the display area is moved in the first direction; and (e) when the first display driver is controlled by the third control signal, the display area is moved in the second direction opposite to the first direction.

Abstract: A driving circuit and operating method thereof are disclosed. The driving circuit is coupled to a display panel. The driving circuit includes a memory. The method includes: (a) the driving circuit receives an image data including N frames, N is a positive integer; (b) during a first period, writing a first frame of image data into the memory along a first direction; and (c) during a second period, reading the first frame from the memory along a second direction and outputting it to the display panel and then writing a second frame of image data into the memory along the second direction. Wherein, since the second period is later then the first period and the second direction is opposite to the first direction, the first frame read from the memory in step (c) and the first frame written into the memory in step (b) are upside down each other.

Abstract: A driving circuit applied to a LCD apparatus is disclosed. The driving circuit includes a channel data line, a reference voltage generation unit, an external storage capacitor, a comparing unit, a switching unit, and an operation unit. The channel data line transmits a data. The reference voltage generation unit generates a reference voltage. A terminal of the external storage capacitor is coupled to ground. The comparing unit compares the reference voltage and a capacitor voltage and outputs a compared result. The switching unit is coupled to another terminal of the external storage capacitor and the channel data line. The operation unit is coupled to the comparing unit, the channel data line, and the switching unit to receive the compared result and a MSB of the data to operate, and to selectively switch on the switching unit.

Abstract: A display driving apparatus is disclosed. The display driving apparatus includes a data processing unit, a first setting unit, a second setting unit, a mapping unit and a source driving unit. The data processing unit receives and processes an image data including data lines. The first setting unit generates a first setting signal corresponding to a first gamma value. The second setting unit generates a second setting signal corresponding to a second gamma value. The mapping unit maps the first gamma value and second gamma value to odd-numbered data lines and even-numbered data lines of the data lines respectively according to the first setting signal and second setting signal. The source driving unit outputs the first gamma value and second gamma value to odd-numbered display lines and even-numbered display lines of display lines of a display panel respectively.

Abstract: A driving circuit applied to a LCD apparatus is disclosed. The driving circuit includes a channel data line, a reference voltage generation unit, an external storage capacitor, a comparing unit, a switching unit, and an operation unit. The channel data line transmits a data. The reference voltage generation unit generates a reference voltage. A terminal of the external storage capacitor is coupled to ground. The comparing unit compares the reference voltage and a capacitor voltage and outputs a compared result. The switching unit is coupled to another terminal of the external storage capacitor and the channel data line. The operation unit is coupled to the comparing unit, the channel data line, and the switching unit to receive the compared result and a MSB of the data to operate, and to selectively switch on the switching unit.

Abstract: A source driver applied in a display includes a DAC and an output buffer. The DAC receives M-bits digital input voltage and converts it into 2M analog input voltages. M is a positive integer. The output buffer with interpolating function receives the 2M analog input voltages and increases them to K analog output voltages in a N-bits interpolating way. N is a positive integer and K=2M*2N=2(M+N). The output buffer includes a positive output buffer unit and a negative output buffer unit and generates a positive interpolating voltage and a negative interpolating voltage through them respectively to share the same source output channel of the source driver and achieve linear interpolation voltage characteristics through mutual compensation between the positive interpolating voltage and the negative interpolating voltage.

Abstract: A driving circuit for an LCD system is provided. The LCD system includes a common electrode, a display electrode, and a capacitor. An AC voltage output terminal of the driving circuit is coupled to the common electrode via the capacitor. The display electrode and a charging/discharging unit in the driving circuit are respectively coupled to the AC voltage output terminal through a switch. According to requirements to change the electrical polarity of the common electrode, a control unit in the driving circuit turns on/off the two switches respectively so as to charge or discharge the AC voltage output terminal.

Abstract: A panel driving device for driving a display panel including N data lines is disclosed. The panel driving device includes a memory array and a source driver. The memory array includes M memory blocks, a controller and an output unit. Each memory block includes N memory units. The controller is configured to divide serial image data into M groups of sub-image data and write each group of sub-image data into the corresponding memory block sequentially, wherein each group of sub-image data has N sub-image data. The output unit is configured to output the data in the M memory blocks sequentially in a time division manner in response to a selection signal. The source driver includes N driving units having the same configuration. After the driving unit receives the time-divided data output from the output unit, signal processing is performed to generate an image signal to be output to the corresponding data line.