Patents by Inventor Jun Ruan

Jun Ruan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190328132
    Abstract: A supporting bracket for supporting a mobile terminal on a platform includes a first bracket body provided with a bearing surface for supporting the mobile terminal and a supporting surface located below the bearing surface and configured for siting on the platform in order to support the bearing surface and changing an angle formed between the platform with the supporting bracket placed thereon and the mobile terminal leaned on the bearing surface. The supporting surface is a curved surface, and the bearing surface is connected with opposite ends of the supporting surface. Therefore, the supporting bracket is simple in structure, convenient to carry and easy to adjust the angle formed between the platform and the mobile terminal leaned on the bearing surface, and easy to be widely used.
    Type: Application
    Filed: June 12, 2018
    Publication date: October 31, 2019
    Inventors: JUN XIAO, XIAOBO WANG, HAIZHEN LI, JIANMING LU, MINGSHUI RUAN, WEICHAO LI, LONG LI
  • Publication number: 20190298057
    Abstract: A combined bracket includes a first bracket and a second bracket, the first bracket and the second bracket are detachably connected. The first bracket includes a first pin and a second pin respectively formed at two ends of the first bracket, and the length of the first pin is larger or smaller than the length of the second pin, making the first pin and the second pin asymmetric. The second bracket is provided with a slot. One of the first pin and the second pin are inserted in the slot and cooperate with one end of the second bracket to form a platform for supporting the mobile device. The other one of the first pin and the second pin and the other end of the second bracket form supporting legs of the combined bracket.
    Type: Application
    Filed: May 28, 2018
    Publication date: October 3, 2019
    Applicant: Futurepath Technology (Shenzhen) Co., Ltd.
    Inventors: Jun XIAO, Xiaobo WANG, Haizhen LI, Jianming LU, Mingshui RUAN
  • Publication number: 20190296571
    Abstract: A charging device for a mobile terminal includes a mobile power supply for charging the mobile terminal and two handles respectively located at two sides of the mobile power supply. The mobile power supply is provided with a retaining member for being detachably connected with the mobile terminal. In use, users can use the handles to operate the mobile terminal, thereby avoiding discomfort of the wrists of the users caused by using the mobile terminal for a long time. The mobile power supply is capable of charging a battery within the mobile terminal to extend life of the battery.
    Type: Application
    Filed: May 28, 2018
    Publication date: September 26, 2019
    Applicant: Futurepath Technology (Shenzhen) Co., Ltd.
    Inventors: Jun XIAO, Xiaobo WANG, Haizhen LI, Jianming LU, Mingshui RUAN
  • Publication number: 20190221986
    Abstract: The present application is applicable to laser technology field and provides a dual-wavelength synchronous pulsed fiber laser based on rare earth ions co-doped fiber, which includes a continuous light LD pumping source, a rare earth ions co-doped fiber and two resonant cavities. Sensitizing ions in the rare earth ions co-doped fiber absorb the pumping light and radiate laser of one wavelength. Meanwhile, sensitized ions in the rare earth ions co-doped fiber radiate laser of another wavelength. Laser generated by sensitizing ions is subjected to Q-switching or mode locking with the saturable absorber inserted in the cavity to generate pulsed laser. Generation and partial reabsorption for the pulsed laser modulates gain of the laser radiated by sensitized ions periodically and generates synchronous pulsed laser, thereby implementing a dual-wavelength synchronous pulsed fiber laser.
    Type: Application
    Filed: March 22, 2019
    Publication date: July 18, 2019
    Inventors: Chunyu Guo, Weiqi Liu, Shuangchen Ruan, Jun Yu, Yewang Chen, Ruoheng Luo, Yihuai Zhu
  • Publication number: 20190151375
    Abstract: Disclosed are an extract that is effective in treating drug addiction and a preparation method therefor. An effective component of the extract has the following chemical structural characteristics: a cholestenol compound with hydroxyl (OH) at position 3 and a double bond between position 5 and position 6, or a cholestenol compound with hydroxyl (OH) at position 3, a double bond between position 5 and position 6 and a double bond between position 22 and position 23. The extract can be extracted from the traditional Chinese medicine Agriolima agrestis. The extract of the present invention is safe in acute toxicity, sedative and hypnotic without physical and psychic dependence, has an inhibitory effect on excitability in mouse caused by morphine and benzedrine and a detoxification treatment effect on the withdrawal symptoms in morphine-dependent rats, and is useful in the development of medications or food for treating drug addiction.
    Type: Application
    Filed: January 28, 2019
    Publication date: May 23, 2019
    Inventor: Jun RUAN
  • Patent number: 10284072
    Abstract: A voltage regulator includes a high-side device, a low-side device, and a controller. The high-side device includes first and second transistors each coupled between an input terminal and an intermediate terminal, where the first transistor has a higher breakdown voltage than the second transistor. The low-side device is coupled between the intermediate terminal and a ground terminal. The controller is configured to drive the high-side and low-side devices to (a) alternately couple the intermediate terminal to the input terminal and the ground terminal and (b) cause the first transistor to control a voltage across the second transistor during switching transitions of the second transistor.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: May 7, 2019
    Assignee: Volterra Semiconductor LLC
    Inventors: Marco A. Zuniga, Chiteh Chiang, Yang Lu, Badredin Fatemizadeh, Amit Paul, Jun Ruan, Craig Cassella
  • Patent number: 10147801
    Abstract: The present application features a transistor that includes an n-well region implanted into a surface of a substrate, a gate region, and a source region, and a drain region. The source region is on a first side of the gate region and includes a p-body region in the n-well region. An n+ region and a p+ region are implanted in the p-body region such that the p+ region is below the n+ region. The drain region is on a second side of the gate region and includes an n+ region.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: December 4, 2018
    Assignee: Volterra Semiconductor LLC
    Inventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
  • Publication number: 20170338731
    Abstract: A voltage regulator includes a high-side device, a low-side device, and a controller. The high-side device includes first and second transistors each coupled between an input terminal and an intermediate terminal, where the first transistor has a higher breakdown voltage than the second transistor. The low-side device is coupled between the intermediate terminal and a ground terminal. The controller is configured to drive the high-side and low-side devices to (a) alternately couple the intermediate terminal to the input terminal and the ground terminal and (b) cause the first transistor to control a voltage across the second transistor during switching transitions of the second transistor.
    Type: Application
    Filed: July 28, 2017
    Publication date: November 23, 2017
    Inventors: Marco A. Zuniga, Chiteh Chiang, Yang Lu, Badredin Fatemizadeh, Amit Paul, Jun Ruan, Craig Cassella
  • Patent number: 9722483
    Abstract: A voltage regulator has an input terminal and a ground terminal. The voltage regulator includes a high-side device, a low side device, and a controller. The high-side device is coupled between the input terminal and an intermediate terminal. The high-side device includes first and second transistors each coupled between the input terminal and the intermediate terminal, such that the first transistor controls a drain-source switching voltage of the second transistor. The low-side device is coupled between the intermediate terminal and the ground terminal. The controller drives the high-side and low-side devices to alternately couple the intermediate terminal to the input terminal and the ground terminal.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: August 1, 2017
    Assignee: Volterra Semiconductor LLC
    Inventors: Marco A. Zuniga, Chiteh Chiang, Yang Lu, Badredin Fatemizadeh, Amit Paul, Jun Ruan, Craig Cassella
  • Patent number: 9178408
    Abstract: This document describes systems and techniques related to voltage regulators. The subject matter of this document can be embodied in a method that includes measuring an output current of a switching regulator. The switching regulator includes a high-side transistor and a low side-transistor wherein the high-side transistor and the low-side transistor are driven using a first gate voltage and a second, different gate voltage, respectively. The method also includes adjusting a direct-current (DC) voltage source of the switching regulator such that the first gate voltage is adjusted in accordance with the measured output current.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 3, 2015
    Assignee: Volterra Semiconductor LLC
    Inventors: Marco A. Zuniga, Chiteh Chiang, William Numann, Yang Lu, Jun Ruan
  • Patent number: 9159804
    Abstract: Described here are transistors and fabrication methods thereof. In one implementation, a transistor includes an n-well region implanted into a surface of a substrate, and a trench in the n-well region. The trench extends from the surface to a first depth. The trench includes a gate of conductive material in the trench, and dielectric material filling a volume of the trench not filled by the conductive material. The transistor also includes a p-type material in a first region extending from a second depth to a third depth, the second depth and the third depth being greater than the first depth. The transistor further includes a source region and a drain region.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: October 13, 2015
    Assignee: Volterra Semiconductor LLC
    Inventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
  • Patent number: 8969158
    Abstract: A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: March 3, 2015
    Assignee: Volterra Semiconductor Corporation
    Inventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
  • Publication number: 20140374826
    Abstract: Described here are transistors and fabrication methods thereof. In one implementation, a transistor includes an n-well region implanted into a surface of a substrate, and a trench in the n-well region. The trench extends from the surface to a first depth. The trench includes a gate of conductive material in the trench, and dielectric material filling a volume of the trench not filled by the conductive material. The transistor also includes a p-type material in a first region extending from a second depth to a third depth, the second depth and the third depth being greater than the first depth. The transistor further includes a source region and a drain region.
    Type: Application
    Filed: September 16, 2014
    Publication date: December 25, 2014
    Inventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
  • Patent number: 8866217
    Abstract: Described here are transistors and fabrication methods thereof. In one implementation, a transistor includes an n-well region implanted into a surface of a substrate, and a trench in the n-well region. The trench extends from the surface to a first depth. The trench includes a gate of conductive material in the trench, and dielectric material filling a volume of the trench not filled by the conductive material. The transistor also includes a p-type material in a first region extending from a second depth to a third depth, the second depth and the third depth being greater than the first depth. The transistor further includes a source region and a drain region.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: October 21, 2014
    Assignee: Volterra Semiconductor LLC
    Inventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
  • Publication number: 20140266113
    Abstract: A voltage regulator has an input terminal and a ground terminal. The voltage regulator includes a high-side device, a low side device, and a controller. The high-side device is coupled between the input terminal and an intermediate terminal. The high-side device includes first and second transistors each coupled between the input terminal and the intermediate terminal, such that the first transistor controls a drain-source switching voltage of the second transistor. The low-side device is coupled between the intermediate terminal and the ground terminal. The controller drives the high-side and low-side devices to alternately couple the intermediate terminal to the input terminal and the ground terminal.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 18, 2014
    Applicant: Volterra Semiconductor Corporation
    Inventors: Marco A. Zuniga, Chiteh Chiang, Yang Lu, Badredin Fatemizadeh, Amit Paul, Jun Ruan, Craig Cassella
  • Publication number: 20140266091
    Abstract: This document describes systems and techniques related to voltage regulators. The subject matter of this document can be embodied in a method that includes measuring an output current of a switching regulator. The switching regulator includes a high-side transistor and a low side-transistor wherein the high-side transistor and the low-side transistor are driven using a first gate voltage and a second, different gate voltage, respectively. The method also includes adjusting a direct-current (DC) voltage source of the switching regulator such that the first gate voltage is adjusted in accordance with the measured output current.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: Volterra Semiconductor Corporation
    Inventors: Marco A. Zuniga, Chiteh Chiang, William Numann, Yang Lu, Jun Ruan
  • Publication number: 20140147979
    Abstract: A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material.
    Type: Application
    Filed: January 28, 2014
    Publication date: May 29, 2014
    Applicant: Volterra Semiconductor Corporation
    Inventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
  • Patent number: 8709899
    Abstract: The present application features methods of fabricating a gate region in a vertical laterally diffused metal oxide semiconductor (LDMOS) transistor. In one aspect, a method includes depositing a masking layer on an n-well region implanted on a substrate, patterning the masking layer to define an area, and forming a first trench in the area such that a length of the first trench extends from a surface of the n-well region to a first depth in the n-well region. The method also includes filling the first trench by a conductive material and depositing a layer of oxide over the area. The method further includes etching out at least a portion of the oxide layer to expose a portion of the conductive material, removing the conductive material from the exposed portion to form a second trench, and filling the second trench with an oxide to form an asymmetric gate of the transistor.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: April 29, 2014
    Assignee: Volterra Semiconductor Corporation
    Inventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan, John Xia
  • Patent number: 8647950
    Abstract: A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: February 11, 2014
    Assignee: Volterra Semiconductor Corporation
    Inventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
  • Publication number: 20130115744
    Abstract: A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material.
    Type: Application
    Filed: August 10, 2012
    Publication date: May 9, 2013
    Applicant: Volterra Semiconductor Corporation
    Inventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan