Patents by Inventor Jun Ruan
Jun Ruan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140374826Abstract: Described here are transistors and fabrication methods thereof. In one implementation, a transistor includes an n-well region implanted into a surface of a substrate, and a trench in the n-well region. The trench extends from the surface to a first depth. The trench includes a gate of conductive material in the trench, and dielectric material filling a volume of the trench not filled by the conductive material. The transistor also includes a p-type material in a first region extending from a second depth to a third depth, the second depth and the third depth being greater than the first depth. The transistor further includes a source region and a drain region.Type: ApplicationFiled: September 16, 2014Publication date: December 25, 2014Inventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
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Patent number: 8866217Abstract: Described here are transistors and fabrication methods thereof. In one implementation, a transistor includes an n-well region implanted into a surface of a substrate, and a trench in the n-well region. The trench extends from the surface to a first depth. The trench includes a gate of conductive material in the trench, and dielectric material filling a volume of the trench not filled by the conductive material. The transistor also includes a p-type material in a first region extending from a second depth to a third depth, the second depth and the third depth being greater than the first depth. The transistor further includes a source region and a drain region.Type: GrantFiled: August 10, 2012Date of Patent: October 21, 2014Assignee: Volterra Semiconductor LLCInventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
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Publication number: 20140266091Abstract: This document describes systems and techniques related to voltage regulators. The subject matter of this document can be embodied in a method that includes measuring an output current of a switching regulator. The switching regulator includes a high-side transistor and a low side-transistor wherein the high-side transistor and the low-side transistor are driven using a first gate voltage and a second, different gate voltage, respectively. The method also includes adjusting a direct-current (DC) voltage source of the switching regulator such that the first gate voltage is adjusted in accordance with the measured output current.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: Volterra Semiconductor CorporationInventors: Marco A. Zuniga, Chiteh Chiang, William Numann, Yang Lu, Jun Ruan
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Publication number: 20140266113Abstract: A voltage regulator has an input terminal and a ground terminal. The voltage regulator includes a high-side device, a low side device, and a controller. The high-side device is coupled between the input terminal and an intermediate terminal. The high-side device includes first and second transistors each coupled between the input terminal and the intermediate terminal, such that the first transistor controls a drain-source switching voltage of the second transistor. The low-side device is coupled between the intermediate terminal and the ground terminal. The controller drives the high-side and low-side devices to alternately couple the intermediate terminal to the input terminal and the ground terminal.Type: ApplicationFiled: March 14, 2014Publication date: September 18, 2014Applicant: Volterra Semiconductor CorporationInventors: Marco A. Zuniga, Chiteh Chiang, Yang Lu, Badredin Fatemizadeh, Amit Paul, Jun Ruan, Craig Cassella
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Publication number: 20140147979Abstract: A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material.Type: ApplicationFiled: January 28, 2014Publication date: May 29, 2014Applicant: Volterra Semiconductor CorporationInventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
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Patent number: 8709899Abstract: The present application features methods of fabricating a gate region in a vertical laterally diffused metal oxide semiconductor (LDMOS) transistor. In one aspect, a method includes depositing a masking layer on an n-well region implanted on a substrate, patterning the masking layer to define an area, and forming a first trench in the area such that a length of the first trench extends from a surface of the n-well region to a first depth in the n-well region. The method also includes filling the first trench by a conductive material and depositing a layer of oxide over the area. The method further includes etching out at least a portion of the oxide layer to expose a portion of the conductive material, removing the conductive material from the exposed portion to form a second trench, and filling the second trench with an oxide to form an asymmetric gate of the transistor.Type: GrantFiled: August 10, 2012Date of Patent: April 29, 2014Assignee: Volterra Semiconductor CorporationInventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan, John Xia
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Patent number: 8647950Abstract: A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material.Type: GrantFiled: August 10, 2012Date of Patent: February 11, 2014Assignee: Volterra Semiconductor CorporationInventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
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Publication number: 20130115744Abstract: A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material.Type: ApplicationFiled: August 10, 2012Publication date: May 9, 2013Applicant: Volterra Semiconductor CorporationInventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
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Publication number: 20130105887Abstract: Described here are transistors and fabrication methods thereof. In one implementation, a transistor includes an n-well region implanted into a surface of a substrate, and a trench in the n-well region. The trench extends from the surface to a first depth. The trench includes a gate of conductive material in the trench, and dielectric material filling a volume of the trench not filled by the conductive material. The transistor also includes a p-type material in a first region extending from a second depth to a third depth, the second depth and the third depth being greater than the first depth. The transistor further includes a source region and a drain region.Type: ApplicationFiled: August 10, 2012Publication date: May 2, 2013Applicant: Volterra Semiconductor CorporationInventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
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Publication number: 20130105888Abstract: The present application features a transistor that includes an n-well region implanted into a surface of a substrate, a gate region, and a source region, and a drain region. The source region is on a first side of the gate region and includes a p-body region in the n-well region. An n+ region and a p+ region are implanted in the p-body region such that the p+ region is below the n+ region. The drain region is on a second side of the gate region and includes an n+ region.Type: ApplicationFiled: August 10, 2012Publication date: May 2, 2013Applicant: Volterra Semiconductor CorporationInventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
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Publication number: 20130109143Abstract: The present application features methods of fabricating a gate region in a vertical laterally diffused metal oxide semiconductor (LDMOS) transistor. In one aspect, a method includes depositing a masking layer on an n-well region implanted on a substrate, patterning the masking layer to define an area, and forming a first trench in the area such that a length of the first trench extends from a surface of the n-well region to a first depth in the n-well region. The method also includes filling the first trench by a conductive material and depositing a layer of oxide over the area. The method further includes etching out at least a portion of the oxide layer to expose a portion of the conductive material, removing the conductive material from the exposed portion to form a second trench, and filling the second trench with an oxide to form an asymmetric gate of the transistor.Type: ApplicationFiled: August 10, 2012Publication date: May 2, 2013Applicant: Volterra Semiconductor CorporationInventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan, John Xia
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Patent number: 7600996Abstract: A safety gas lighter with a loosely mounted striking wheel, comprises a lighter body, topped by a lighter head, an gas release valve, a pressing lever for gas release, a spring, a flint, and a wheel assembly with an axle. The diameter of the axle integrated with the first side wheel is smaller than the diameter of the inner opening of the striking wheel, and the diameter of side wheels are larger than diameter of striking wheel. When in use, because and the diameter of side wheels are larger than diameter of striking wheel, the thumb would strike the side wheels first. For children, because their hands are small, and their strengths cannot be compared with the adults, they can only rotate side wheels, but cannot rotate steel wheels, so the children cannot light fire using the lighter. When adults are using the lighter, their hands will strike the side wheels as well as the striking wheel, to make the side wheels and striking wheel rotate simultaneously.Type: GrantFiled: June 14, 2005Date of Patent: October 13, 2009Assignee: Toyo Lighter Co.Inventor: Jun Jun Ruan
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Publication number: 20090104574Abstract: A utility lighter includes a housing having an elongated tube portion, an actuation button depressibly mounted at a housing portion of the housing, a safety wheel rotated and mounted at the actuation button, and a blocker driven to move by a rotational movement of the safety wheel between an inoperative configuration and an operative configuration. In the inoperative configuration, the blocker is retained in the housing portion of the housing to prevent a depressible head of a piezoelectric element from being depressed by the actuation button for ignition. In the operative configuration, the safety wheel is rotated at the actuation button to drive the blocker to diminish undesirable position, so that the actuation button is depressed to depress the depressible head of the piezoelectric element and to actuate the valve actuator for ignition.Type: ApplicationFiled: October 22, 2007Publication date: April 23, 2009Inventor: Jun Jun RUAN
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Patent number: 7462543Abstract: A method for forming an NMOS transistor for use in a flash memory cell on a P-type semiconductor structure includes forming a photoresist layer over the semiconductor structure and patterning the photoresist layer using a source/drain mask for the NMOS transistor; forming a first N-type region and a second N-type region by a first implantation process using the patterned photoresist as an implant mask where the first implantation process uses a high implant dose at a low implant energy and the first and second N-type regions form the source and drain regions of the NMOS transistor; forming a channel doped region by a second implantation process using the patterned photoresist as an implant mask where the second implantation process uses a low implant dose at a high implant energy and the channel doped region is formed for adjusting a threshold voltage of the NMOS transistor.Type: GrantFiled: December 7, 2007Date of Patent: December 9, 2008Assignee: Micrel, Inc.Inventor: Jun Ruan
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Publication number: 20060281034Abstract: A safety gas lighter with a loosely mounted striking wheel, comprises a lighter body, topped by a lighter head, an gas release valve, a pressing lever for gas release, a spring, a flint, and a wheel assembly with an axle. The diameter of the axle integrated with the first side wheel is smaller than the diameter of the inner opening of the striking wheel, and the diameter of side wheels are larger than diameter of striking wheel. When in use, because and the diameter of side wheels are larger than diameter of striking wheel, the thumb would strike the side wheels first. For children, because their hands are small, and their strengths cannot be compared with the adults, they can only rotate side wheels, but cannot rotate steel wheels, so the children cannot light fire using the lighter. When adults are using the lighter, their hands will strike the side wheels as well as the striking wheel, to make the side wheels and striking wheel rotate simultaneously.Type: ApplicationFiled: June 14, 2005Publication date: December 14, 2006Inventor: Jun Ruan
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Publication number: 20060281035Abstract: A safety gas lighter with a loosely mounted striking wheel, comprises a lighter body, topped by a lighter head, an gas release valve, a pressing lever for gas release, a spring, a flint, and a wheel assembly with an axle. The diameter of the axle integrated with the first side wheel is smaller than the diameter of the inner opening of the striking wheel, and the diameter of side wheels are larger than diameter of striking wheel. When in use, because and the diameter of side wheels are larger than diameter of striking wheel, the thumb would strike the side wheels. For children, because their hands are small, and their strengths cannot be compared with the adults, they can only rotate side wheels, but cannot rotate striking wheels, so the children cannot light fire using the lighter. When adults are using the lighter, they will be able to rotate the side wheels as well as the striking wheel. The striking wheel will touch the flint, to generate sparks, and light fires.Type: ApplicationFiled: May 10, 2006Publication date: December 14, 2006Inventor: Jun Ruan
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Patent number: D539471Type: GrantFiled: May 26, 2006Date of Patent: March 27, 2007Inventor: Jun Jun Ruan