Patents by Inventor Jun Sakakibara

Jun Sakakibara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040223196
    Abstract: There is disclosed an image reading apparatus having an image sensor unit. The image sensor unit may include a number of photodiode arrays. The photodiode arrays may have different qualities and the output of the photodiode arrays may be processed differently. Output of the photodiode arrays may be mixed to improve image qualities.
    Type: Application
    Filed: March 9, 2004
    Publication date: November 11, 2004
    Inventors: Koji Tanimoto, Jun Sakakibara, Yoshikatsu Kamisuwa, Kunihiko Miura
  • Patent number: 6812948
    Abstract: In a digital copying machine using a multi-beam optical system, a sensor pattern senses a light beam directed onto the photosensitive drum and generates current according to the amount of light. The current is converted into a voltage by an operational amplifier acting as a current/voltage conversion amplifier. The output voltage of the operational amplifier is integrated by an integrator. The output of the integrator is converted into a digital signal by an A/D converter, thereby producing luminous energy sensing information. According to the luminous energy sensing information, a laser oscillator is controlled. Between the operational amplifier and integrator, a variable resistor is inserted which absorbs variations in the sensitivity of the sensor pattern or variations in the conversion characteristic of the operational amplifier.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: November 2, 2004
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Tec Kabushiki Kaisha
    Inventors: Kenichi Komiya, Koji Tanimoto, Jun Sakakibara, Naoaki Ide, Toshimitsu Ichiyanagi
  • Publication number: 20040196514
    Abstract: There is disclosed an image reading apparatus having an image sensor unit. The image sensor unit may include a number of photodiode arrays. The photodiode arrays may have different qualities and the output of the photodiode arrays may be processed differently. Output of the photodiode arrays may be mixed to improve image qualities.
    Type: Application
    Filed: January 30, 2004
    Publication date: October 7, 2004
    Inventors: Koji Tanimoto, Jun Sakakibara, Yoshikatsu Kamisuwa, Kunihiko Miura
  • Publication number: 20040184116
    Abstract: All electric charges accumulated in a line sensor are transferred via a first shift gate to a first analog shift register. By controlling the width of a shift pulse signal to be supplied to a second shift gate, the amount of an electric charge transfer when the electric charges on the first analog shift register are transferred to a second shift register is controlled. As a result, the amount of the electric charges on the first analog shift register is controlled to a desired value. Accordingly, the amplitude of an image signal outputted from the first analog shift register can be easily adjusted. Further, the sensitivity of a CCD line sensor and variation of light amount of a light source can be corrected.
    Type: Application
    Filed: March 20, 2003
    Publication date: September 23, 2004
    Applicant: TOSHIBA TEC KABUSHIKI KAISHA
    Inventors: Jun Sakakibara, Koji Tanimoto
  • Publication number: 20040174576
    Abstract: Methods and apparatus for color signal compensation are disclosed. A quality of one type of signal is enhanced using a second type of signal, wherein the second type of signal has a higher quality than that of the unenhanced first type of signal. This may be used in an image forming apparatus for scanning a color image, and using higher-resolution monochrome signals to enhance the resolution of lower-resolution color signals.
    Type: Application
    Filed: March 2, 2004
    Publication date: September 9, 2004
    Inventors: Yoshikatsu Kamisuwa, Koji Tanimoto, Jun Sakakibara, Kunihiko Miura
  • Publication number: 20040174447
    Abstract: A 4-line CCD sensor according to one embodiment of the present invention has a monochromic reading line sensor section and a color reading line sensor section. This 4-line CCD sensor is characterized in that amplification factors for amplifiers 1 to 4 are set so that the amplitude of an output signal from the monochromic reading line sensor section is the same as that of each output signal from the color reading line sensor section. This 4-line CCD sensor is characterized in that the amplification factors for the amplifiers 1 to 4 are set so that the amplitude of each output signal from the color reading line sensor section is smaller than that of an output signal from the monochromic reading line sensor section.
    Type: Application
    Filed: March 4, 2003
    Publication date: September 9, 2004
    Applicant: TOSHIBA TEC KABUSHIKI KAISHA
    Inventors: Jun Sakakibara, Koji Tanimoto
  • Publication number: 20040119091
    Abstract: A semiconductor device includes a base P region, a source N+ region, and a drain N+ region formed in a surface layer portion on a principal surface in an N− silicon layer. In the surface layer portion on the principal surface, an N well region is formed deeper than the drain N+ region in a region including the drain N+ region and is in contact with the base P region. A trench is formed so as to penetrate the base P region in a direction toward the drain N+ region from the source N+ region as a planar structure. A gate electrode is formed via a gate insulating film in the inside of the trench.
    Type: Application
    Filed: December 9, 2003
    Publication date: June 24, 2004
    Applicant: DENSO CORPORATION
    Inventors: Naohiro Suzuki, Jun Sakakibara, Yoshitaka Noda, Hitoshi Yamaguchi
  • Publication number: 20040089896
    Abstract: A first trench is formed in a surface of an n+-type semiconductor substrate that forms a source region. A p-type base region, an n−-type drift region, and an n+-type drain region are deposited in this order in the first trench using epitaxial growth. A second trench extending from the source region to the drift region through the base region is formed in the surface. A gate insulating film and a gate electrode are formed on a surface defining the second trench. The n+-type drain region has a location where growing surfaces come together in epitaxial growth and where a defect is likely to occur, and the gate electrode lacks such a location and thus avoids an increase in normalized ON resistance. Therefore, the breakdown voltage remains high without increasing the ON resistance.
    Type: Application
    Filed: October 30, 2003
    Publication date: May 13, 2004
    Inventor: Jun Sakakibara
  • Patent number: 6710793
    Abstract: In an image forming apparatus such as a digital copying machine using a multi-beam optical system, a printing area can be set in the unit equal to or smaller than a clock for image formation by use of a delay pulse for each light beam and the exposure position in the light beam scanning direction (main scanning direction) is always precisely controlled by selecting an optimum set value while the actual light beam position is being checked by use of a sensor.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: March 23, 2004
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Tec Kabushiki Kaisha
    Inventors: Koji Tanimoto, Kenichi Komiya, Daisuke Ishikawa, Koji Kawai, Jun Sakakibara
  • Patent number: 6696323
    Abstract: In a semiconductor device, a p-type base region is provided in an n−-type substrate to extend from a principal surface of the substrate in a perpendicular direction to the principal surface. An n+-type source region extends in the p-type base region from the principal surface in the perpendicular direction, and an n+-type drain region extends in the substrate separately from the p-type base region with a drift region interposed therebetween. A trench is formed to penetrate the p-type base region from the n+-type source region in a direction parallel to the principal surface. A gate electrode is formed in the trench through a gate insulating film. Accordingly, a channel region can be formed with a channel width in a depth direction of the trench when a voltage is applied to the gate electrode.
    Type: Grant
    Filed: January 13, 2003
    Date of Patent: February 24, 2004
    Assignee: Denso Corporation
    Inventors: Hitoshi Yamaguchi, Toshio Sakakibara, Jun Sakakibara, Takumi Shibata, Toshiyuki Morishita
  • Patent number: 6677974
    Abstract: A synchronization signal detector receives a laser beam each time it is scanned in a main scanning direction, and detects a synchronization signal from the received laser beam. An external circuit or the like sets a binary value-determining level for this detector. The binary value-determining level is so determined as not to generate a signal arising from stray light. By this determination, a synchronization error, which is due to stray light, is prevented without adding manufacturing steps to prevent the stray light or without incurring an increase in the cost needed for structural components.
    Type: Grant
    Filed: March 21, 2001
    Date of Patent: January 13, 2004
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Tec Kabushiki Kaisha
    Inventors: Jun Sakakibara, Koji Tanimoto, Kenichi Komiya, Koji Kawai
  • Patent number: 6670673
    Abstract: A first trench is formed in a surface of an n+-type semiconductor substrate that forms a source region. A p-type base region, an n−-type drift region, and an n+-type drain region are deposited in this order in the first trench using epitaxial growth. A second trench extending from the source region to the drift region through the base region is formed in the surface. A gate insulating film and a gate electrode are formed on a surface defining the second trench. The n+-type drain region has a location where growing surfaces come together in epitaxial growth and where a defect is likely to occur, and the gate electrode lacks such a location and thus avoids an increase in normalized ON resistance. Therefore, the breakdown voltage remains high without increasing the ON resistance.
    Type: Grant
    Filed: April 10, 2002
    Date of Patent: December 30, 2003
    Assignee: Denso Corporation
    Inventor: Jun Sakakibara
  • Publication number: 20030219933
    Abstract: A semiconductor device includes a semiconductor substrate and a semiconductor layer. The semiconductor substrate has a main surface that is an Si{100} surface. The substrate has a trench in the main surface. The semiconductor layer is located on surfaces defining the trench to have common crystallographic planes with the semiconductor substrate. The trench is defined by a bottom surface, two long sidewall surfaces that face each other, and two short sidewall surfaces that face each other. The bottom surface and the long sidewall surfaces are Si{100} surfaces.
    Type: Application
    Filed: May 21, 2003
    Publication date: November 27, 2003
    Inventors: Shoichi Yamauchi, Hitoshi Yamaguchi, Jun Sakakibara, Nobuhiro Tsuji
  • Patent number: 6646668
    Abstract: An image forming apparatus maintains a constant beam scanning state so that light beams scan each drum always in the same state once a desired color overlapping accuracy is obtained by controlling color registration in color image formation. This mechanism achieves constantly fine color overlapping without forming a test pattern several times or consuming toner unnecessarily. A beam passage switch is provided in a laser scanning system. Sensors provided near each photosensitive drum determine whether each light beam has scanned a certain portion with no inclination or a certain scanning area, or whether each image magnification provides a desired size.
    Type: Grant
    Filed: June 17, 2002
    Date of Patent: November 11, 2003
    Assignees: Kabushiki Kaisha Toshiba, Toshiba TEC Kabushiki Kaisha
    Inventors: Koji Tanimoto, Kenichi Komiya, Jun Sakakibara, Koji Kawai
  • Publication number: 20030141514
    Abstract: In a semiconductor device, a p-type base region is provided in an n−-type substrate to extend from a principal surface of the substrate in a perpendicular direction to the principal surface. An n+-type source region extends in the p-type base region from the principal surface in the perpendicular direction, and an n+-type drain region extends in the substrate separately from the p-type base region with a drift region interposed therebetween. A trench is formed to penetrate the p-type base region from the n+-type source region in a direction parallel to the principal surface. A gate electrode is formed in the trench through a gate insulating film. Accordingly, a channel region can be formed with a channel width in a depth direction of the trench when a voltage is applied to the gate electrode.
    Type: Application
    Filed: January 13, 2003
    Publication date: July 31, 2003
    Inventors: Hitoshi Yamaguchi, Toshio Sakakibara, Jun Sakakibara, Takumi Shibata, Toshiyuki Morishita
  • Patent number: 6570239
    Abstract: A trench is formed in an n+ type substrate in a vertical direction from a main surface of the substrate, and a p type layer is deposited in the trench to have a recess portion. An n+ type layer is embedded in the recess portion. Accordingly, the p type layer is formed, as a resistive element, into a U-shape with ends that are ended on the main surface of the substrate. The resistive element has a resistance length corresponding to a path of the U-shape.
    Type: Grant
    Filed: March 13, 2001
    Date of Patent: May 27, 2003
    Assignee: Denso Corporation
    Inventors: Jun Sakakibara, Hitoshi Yamaguchi
  • Patent number: 6549265
    Abstract: The emission level of a laser source at the non-imaging time when image data “0” is input and the emission level at the imaging time when image data “1” is input are controlled so that each of them becomes a desired level. The light output intensity is stabilized at all times regardless of variations in ambient temperature. As a result, images uniform in density can be obtained.
    Type: Grant
    Filed: September 14, 2000
    Date of Patent: April 15, 2003
    Assignee: Toshiba Tec Kabushiki Kaisha
    Inventors: Jun Sakakibara, Koji Tanimoto, Kenichi Komiya, Toshimitsu Ichiyanagi, Naoaki Ide, Koji Kawai
  • Publication number: 20030053157
    Abstract: A four-line CCD sensor is structured by line sensors R, G, B in which color filters are respectively disposed on surfaces of light receiving elements, and a line sensor BK at which no color filter is disposed. Amplitudes of signals which are outputted from the line sensors R, G, B at a time of reading a color document, and an amplitude of a signal which is outputted from the line sensor BK at a time of reading a monochrome document are adjusted so as to be substantially equal to one another. In a case in which a color document is read, outputs of the line sensors R, G, B are selectively provided, and in a case in which a monochrome document is read, output of the line sensor BK is selectively provided.
    Type: Application
    Filed: September 19, 2001
    Publication date: March 20, 2003
    Inventors: Jun Sakakibara, Koji Tanimoto
  • Patent number: 6525375
    Abstract: In a semiconductor device, a p-type base region is provided in an n−-type substrate to extend from a principal surface of the substrate in a perpendicular direction to the principal surface. An n+-type source region extends in the p-type base region from the principal surface in the perpendicular direction, and an n+-type drain region extends in the substrate separately from the p-type base region with a drift region interposed therebetween. A trench is formed to penetrate the p-type base region from the n+-type source region in a direction parallel to the principal surface. A gate electrode is formed in the trench through a gate insulating film. Accordingly, a channel region can be formed with a channel width in a depth direction of the trench when a voltage is applied to the gate electrode.
    Type: Grant
    Filed: October 16, 2000
    Date of Patent: February 25, 2003
    Assignee: Denso Corporation
    Inventors: Hitoshi Yamaguchi, Toshio Sakakibara, Jun Sakakibara, Takumi Shibata, Toshiyuki Morishita
  • Patent number: 6509921
    Abstract: Two sawtooth sensor patterns are combined so that they engage with each other. These sensor patterns are arranged so that a light beam passes sawtooth portions in a horizontal scan direction. A light beam's scan position is determined by integrating a difference between output signals from these sensor patterns. It is possible to provide a highly sensitive circuit for processing signals from the sensors and to improve detection accuracy for light beams.
    Type: Grant
    Filed: March 26, 2001
    Date of Patent: January 21, 2003
    Assignee: Toshiba Tec Kabushiki Kaisha
    Inventors: Kenichi Komiya, Koji Tanimoto, Jun Sakakibara, Koji Kawai