Patents by Inventor Jun Satoh
Jun Satoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7165151Abstract: To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.Type: GrantFiled: December 14, 2004Date of Patent: January 16, 2007Assignee: Renesas Technology Corp.Inventors: Kazushige Ayukawa, Seiji Miura, Jun Satoh, Takao Watanabe, Kazumasa Yanagisawa, Yusuke Kanno, Hiroyuki Mizuno
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Publication number: 20060202992Abstract: In a data processor and a shading apparatus used in the data processor, the data processor selects an address based on the information of a memory or a translation look-aside buffer. Therefore, even when the same data are accessed, a different address at high speed is adopted according to the hardware, object to be processed, processing, etc. A plurality of geometric vectors are given as the parameters for the vertexes of a picture, the vectors are interpolated in the picture, and the luminance of each small area in the figure is calculated using the vectors generated by the interpolation. Therefore, a spotlight or highlight can be expressed with high accuracy and at high speed even when the amount of the hardware and the extent of the picture are small.Type: ApplicationFiled: May 12, 2006Publication date: September 14, 2006Inventors: Yasuhiro Nakatsuka, Shigeru Matsuo, Jun Satoh, Masanori Miyoshi, Koyo Katsura, Takashi Sone
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Patent number: 7064756Abstract: In a data processor and a shading apparatus used in the data processor, the data processor selects an address based on the information of a memory or a translation look-aside buffer. Therefore, even when the same data are accessed, a different address at high speed is adopted according to the hardware, object to be processed, processing, etc. A plurality of geometric vectors are given as the parameters for the vertexes of a picture, the vectors are interpolated in the picture, and the luminance of each small area in the figure is calculated using the vectors generated by the interpolation. Therefore, a spotlight or highlight can be expressed with high accuracy and at high speed even when the amount of the hardware and the extent of the picture are small.Type: GrantFiled: September 23, 2004Date of Patent: June 20, 2006Assignee: Renesas Technology CorporationInventors: Yasuhiro Nakatsuka, Shigeru Matsuo, Jun Satoh, Masanori Miyoshi, Koyo Katsura, Takashi Sone
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Publication number: 20060052544Abstract: Disclosed is a method for producing a propylene-based resin composition comprising: a first step of producing a first resin composition (MB) by melt-kneading a first-propylene polymer (A-I) and a fibrous inorganic filler (B) in a weight ratio of (A-I) to (B) of from 3/7 to 7/3; and a second step of producing a second resin composition by adding a second propylene polymer (A-II), a non-fibrous inorganic filler (C) and an elastomer (D) selected from the group consisting of olefin-based elastomer and vinyl aromatic compound-containing elastomer to the first resin composition (MB), followed by melt-kneading them.Type: ApplicationFiled: August 17, 2005Publication date: March 9, 2006Inventors: Tsuyoshi Watanabe, Takashi Sanada, Jun Satoh
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Patent number: 6911497Abstract: A polypropylene resin composition having a melt flow rate of 70 to 120 g/10 min (at 230° C., 2.16 kgf-load), a flexural modulus of 1300 to 4000 MPa and an IZOD impact strength of 30 to 100 kJ/m2, wherein the composition is obtained by adding a small amount of an organic peroxide to a mixture comprising 60 to 80% by weight of a specific propylene-ethylene block copolymer made up of a propylene homopolymer portion and a propylene-ethylene random copolymer portion, a rubber which is a copolymer of ethylene and at least one ?-olefin having a melt flow rate of 2 to 10 g/10 min (at 190° C., 2.16 kgf-load), and inorganic filler (C), and kneading the combined ingredients at a temperature of 170 to 280° C.Type: GrantFiled: March 23, 2004Date of Patent: June 28, 2005Assignee: Sumitomo Chemical Company, LimitedInventors: Jun Satoh, Hiroyuki Tanimura, Katsuyuki Imigi
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Publication number: 20050099876Abstract: To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.Type: ApplicationFiled: December 14, 2004Publication date: May 12, 2005Inventors: Kazushige Ayukawa, Seiji Miura, Jun Satoh, Takao Watanabe, Kazumasa Yanagisawa, Yusuke Kanno, Hiroyuki Mizuno
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Publication number: 20050041489Abstract: In a data processor and a shading apparatus used in the data processor, the data processor selects an address based on the information of a memory or a translation look-aside buffer. Therefore, even when the same data are accessed, a different address at high speed is adopted according to the hardware, object to be processed, processing, etc. A plurality of geometric vectors are given as the parameters for the vertexes of a picture, the vectors are interpolated in the picture, and the luminance of each small area in the figure is calculated using the vectors generated by the interpolation. Therefore, a spotlight or highlight can be expressed with high accuracy and at high speed even when the amount of the hardware and the extent of the picture are small.Type: ApplicationFiled: September 23, 2004Publication date: February 24, 2005Applicant: RENESAS TECHNOLOGY CORPORATIONInventors: Yasuhiro Nakatsuka, Shigeru Matsuo, Jun Satoh, Masanori Miyoshi, Koyo Katsura, Takashi Sone
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Patent number: 6847578Abstract: To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.Type: GrantFiled: December 9, 2003Date of Patent: January 25, 2005Assignee: Renesas Technology Corp.Inventors: Kazushige Ayukawa, Seiji Miura, Jun Satoh, Takao Watanabe, Kazumasa Yanagisawa, Yusuke Kanno, Hiroyuki Mizuno
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Publication number: 20040263523Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.Type: ApplicationFiled: July 23, 2004Publication date: December 30, 2004Applicant: Hitachi, Ltd.Inventors: Jun Satoh, Kazushige Yamagishi, Keisuke Nakashima, Koyo Katsura, Takashi Miyamoto, Mitsuru Watabe, Kenichiroh Ohmura
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Publication number: 20040242773Abstract: A polypropylene resin composition having a melt flow rate of 70 to 120 g/10 min (at 230° C., 2.16 kgf-load), a flexural modulus of 1300 to 4000 MPa and an IZOD impact strength of 30 to 100 kJ/m2, wherein the composition is obtained by adding a small amount of an organic peroxide to a mixture comprising 60 to 80% by weight of a specific propylene-ethylene block copolymer made up of a propylene homopolymer portion and a propylene-ethylene random copolymer portion, a rubber which is a copolymer of ethylene and at least one &agr;-olefin having a melt flow rate of 2 to 10 g/10 min (at 190° C., 2.16 kgf-load), and inorganic filler (C), and kneading the combined ingredients at a temperature of 170 to 280° C.Type: ApplicationFiled: March 23, 2004Publication date: December 2, 2004Applicant: SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Jun Satoh, Hiroyuki Tanimura, Katsuyuki Imigi
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Patent number: 6806875Abstract: In a data processor and a shading apparatus used in the data processor, the data processor selects an address based on the information of a memory or a translation look-aside buffer. Therefore, even when the same data are accessed, a different address at high speed is adopted according to the hardware, object to be processed, processing, etc. A plurality of geometric vectors are given as the parameters for the vertexes of a picture, the vectors are interpolated in the picture, and the luminance of each small area in the figure is calculated using the vectors generated by the interpolation. Therefore, a spotlight or highlight can be expressed with high accuracy and at high speed even when the amount of the hardware and the extent of the picture are small.Type: GrantFiled: June 21, 2002Date of Patent: October 19, 2004Assignee: Renesas Technology Corp.Inventors: Yasuhiro Nakatsuka, Shigeru Matsuo, Jun Satoh, Masanori Miyoshi, Koyo Katsura, Takashi Sone
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Patent number: 6789210Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.Type: GrantFiled: January 30, 2003Date of Patent: September 7, 2004Assignee: Renesas Technology Corp.Inventors: Jun Satoh, Kazushige Yamagishi, Keisuke Nakashima, Koyo Katsura, Takashi Miyamoto, Mitsuru Watabe, Kenichiroh Ohmura
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Patent number: 6785833Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.Type: GrantFiled: February 20, 2003Date of Patent: August 31, 2004Assignee: Renesas Technology Corp.Inventors: Jun Satoh, Kazushige Yamagishi, Keisuke Nakashima, Koyo Katsura, Takashi Miyamoto, Mitsuru Watabe, Kenichiroh Ohmura
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Publication number: 20040114451Abstract: To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.Type: ApplicationFiled: December 9, 2003Publication date: June 17, 2004Inventors: Kazushige Ayukawa, Seiji Miura, Jun Satoh, Takao Watanabe, Kazumasa Yanagisawa, Yusuke Kanno, Hiroyuki Mizuno
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Patent number: 6708249Abstract: To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.Type: GrantFiled: March 20, 2002Date of Patent: March 16, 2004Assignee: Hitachi, Ltd.Inventors: Kazushige Ayukawa, Seiji Miura, Jun Satoh, Takao Watanabe, Kazumasa Yanagisawa, Yusuke Kanno, Hiroyuki Mizuno
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Publication number: 20030126353Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.Type: ApplicationFiled: February 20, 2003Publication date: July 3, 2003Applicant: Hitachi, Ltd.Inventors: Jun Satoh, Kazushige Yamagishi, Keisuke Nakashima, Koyo Katsura, Takashi Miyamoto, Mitsuru Watabe, Kenichiroh Ohmura
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Publication number: 20030115496Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.Type: ApplicationFiled: January 30, 2003Publication date: June 19, 2003Applicant: Hitachi, Ltd.Inventors: Jun Satoh, Kazushige Yamagishi, Keisuke Nakashima, Koyo Katsura, Takashi Miyamoto, Mitsuru Watabe, Kenichiroh Ohmura
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Patent number: 6550014Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.Type: GrantFiled: August 12, 2002Date of Patent: April 15, 2003Assignee: Hitachi, Ltd.Inventors: Jun Satoh, Kazushige Yamagishi, Keisuke Nakashima, Koyo Katsura, Takashi Miyamoto, Mitsuru Watabe, Kenichiroh Ohmura
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Publication number: 20020190992Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.Type: ApplicationFiled: August 12, 2002Publication date: December 19, 2002Applicant: Hitachi, Ltd.Inventors: Jun Satoh, Kazushige Yamagishi, Keisuke Nakashima, Koyo Katsura, Takashi Miyamoto, Mitsuru Watabe, Kenichiroh Ohmura
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Publication number: 20020154116Abstract: In a data processor and a shading apparatus used in the data processor, the data processor selects an address based on the information of a memory or a translation look-aside buffer. Therefore, even when the same data are accessed, a different address at high speed is adopted according to the hardware, object to be processed, processing, etc. A plurality of geometric vectors are given as the parameters for the vertexes of a picture, the vectors are interpolated in the picture, and the luminance of each small area in the figure is calculated using the vectors generated by the interpolation. Therefore, a spotlight or highlight can be expressed with high accuracy and at high speed even when the amount of the hardware and the extent of the picture are small.Type: ApplicationFiled: June 21, 2002Publication date: October 24, 2002Inventors: Yasuhiro Nakatsuka, Shigeru Matsuo, Jun Satoh, Masanori Miyoshi, Koyo Katsura, Takashi Sone