Abstract: Block transfer of neuron output values through data memory for neurosynaptic processors is provided, which in some embodiments includes time-multiplexing. A neurosynaptic core is adapted to apply a plurality of synaptic weights to a plurality of input activations to produce a plurality of output activations. Synaptic weights for one of a plurality of logical cores are read. The neurosynaptic core is configured to implement the one of the plurality of logical cores using the synaptic weights. At least one data block is provided as contiguous input activations to the neurosynaptic core. The input activations are processed by the neurosynaptic core to determine at least one contiguous block of output activations.

Abstract: Simulation and validation of neural network systems is provided. In various embodiments, a description of an artificial neural network is read. A directed graph is constructed comprising a plurality of edges and a plurality of nodes, each of the plurality of edges corresponding to a queue and each of the plurality of nodes corresponding to a computing function of the neural network system. A graph state is updated over a plurality of time steps according to the description of the neural network, the graph state being defined by the contents of each of the plurality of queues. Each of a plurality of assertions is tested at each of the plurality of time steps, each of the plurality of assertions being a function of a subset of the graph state. Invalidity of the neural network system is indicated for each violation of one of the plurality of assertions.

Abstract: Networks of distributed neural cores are provided with hierarchical parallelism. In various embodiments, a plurality of neural cores is provided. Each of the plurality of neural cores comprises a plurality of vector compute units configured to operate in parallel. Each of the plurality of neural cores is configured to compute in parallel output activations by applying its plurality of vector compute units to input activations. Each of the plurality of neural cores is assigned a subset of output activations of a layer of a neural network for computation. Upon receipt of a subset of input activations of the layer of the neural network, each of the plurality of neural cores computes a partial sum for each of its assigned output activations, and computes its assigned output activations from at least the computed partial sums.

Abstract: A neural inference chip includes a global weight memory; a neural core; and a network connecting the global weight memory to the at least one neural core. The neural core comprises a local weight memory. The local weight memory comprises a plurality of memory banks. Each of the plurality of memory banks is uniquely addressable by at least one index. The neural inference chip is adapted to store in the global weight memory a compressed weight block comprising at least one compressed weight matrix. The neural inference chip is adapted to transmit the compressed weight block from the global weight memory to the core via the network. The core is adapted to decode the at least one compressed weight matrix into a decoded weight matrix and store the decoded weight matrix in its local weight memory. The at core is adapted to apply the decoded weight matrix to a plurality of input activations to produce a plurality of output activations.

Abstract: Conflict-free, stall-free, broadcast networks on neural inference chips are provided. In various embodiments, a neural inference chip comprises a plurality of network nodes and a network on chip interconnecting the plurality of network nodes. The network comprises at least one pair of directional paths. The paths of each pair have opposite directions and a common end. The network is configured to accept data at any of the plurality of nodes. The network is configured to propagate data along a first of the pair of directional paths from a source node to the common end of the pair of directional paths and along a second of the pair of directional paths from the common end of the pair of directional paths to one or more destination node.

Abstract: Multi-agent instruction execution engines for neural inference processing are provided. In various embodiments, a neural core is provided. The neural core includes an instruction memory. The instruction memory comprises a plurality of instruction streams, each instruction stream associated with one of a plurality of agents. The instruction memory further comprises a plurality of shared functional units. The neural core is adapted to concurrently execute the plurality of instruction streams on the plurality of associated agents. The execution includes maintaining a separate program counter for each of the plurality of agents, determining a plurality of operations from the instructions of each instruction stream, and directing the operations to the shared functional units. The instructions of each instruction stream are statically scheduled prior to runtime to ensure their execution is conflict free.

Abstract: A neural inference chip is provided, including at least one neural inference core. The at least one neural inference core is adapted to apply a plurality of synaptic weights to a plurality of input activations to produce a plurality of intermediate outputs. The at least one neural inference core comprises a plurality of activation units configured to receive the plurality of intermediate outputs and produce a plurality of activations. Each of the plurality of activation units is configured to apply a configurable activation function to its input. The configurable activation function has at least a re-ranging term and a scaling term, the re-ranging term determining the range of the activations and the scaling term determining the scale of the activations. Each of the plurality of activations units is configured to obtain the re-ranging term and the scaling term from one or more look up tables.

Abstract: Mapping of neural network layers to physical neural cores is provided. In various embodiments, a neural network description describing a plurality of neural network layers is read. Each of the plurality of neural network layers has an associated weight tensor, input tensor, and output tensor. A plurality of precedence relationships among the plurality of neural network layers is determined. The weight tensor, input tensor, and output tensor of each of the plurality of neural network layers are mapped onto an array of neural cores.

Abstract: Provided is a tire rubber composition and a tire each having excellent overall performance in terms of abrasion resistance and crack growth resistance. The tire rubber composition contains a rubber component including an epoxidized diene-based rubber; a divalent or higher carboxylic acid compound; and sulfur, the tire rubber composition containing the sulfur in an amount of 1.0 parts by mass or more per 100 parts by mass of the rubber component, the tire rubber composition having a ratio K (amount of divalent or higher carboxylic acid compound/amount of sulfur) of an amount (parts by mass) of the divalent or higher carboxylic acid compound to an amount (parts by mass) of the sulfur of 0.10 or higher and 10.00 or lower.

Abstract: According to embodiments of the present disclosure, processor chips adapted for efficient massively-concurrent conditional computation are provided. In various embodiments, a chip comprises at least one processing core; a controller operatively coupled to the at least one processing core; and an instruction memory in communication with the controller. The controller is configured to: concurrently compute a plurality of relational operators on a plurality of inputs, resulting in a plurality of results; combine the plurality of results to determine an index; select an operation based on the index; and cause the at least one processing core to execute the selected operation.

Abstract: Systems for neural network computation are provided. A neural network processor comprises a plurality of neural cores. The neural network processor has one or more processor precisions per activation. The processor is configured to accept data having a processor feature dimension. A transformation circuit is coupled to the neural network processor, and is adapted to: receive an input data tensor having an input precision per channel at one or more features; transform the input data tensor from the input precision to the processor precision; divide the input data into a plurality of blocks, each block conforming to one of the processor feature dimensions; provide each of the plurality of blocks to one of the plurality of neural cores. The neural network processor is adapted to compute, by the plurality of neural cores, output of one or more neural network layers.

Abstract: Networks for distributing parameters and data to neural network compute cores. In various embodiments, a neural inference chip comprises a plurality of neural cores and at least one network interconnecting the plurality of neural cores. Each of the plurality of neural cores is adapted to apply a plurality of synaptic weights to a plurality of input activations to produce a plurality of output activations. The at least one network is adapted to simultaneously deliver synaptic weights and/or input activations to the plurality of neural cores.

Abstract: A vehicle bottom structure includes a suspension system, a first undercover, and a second undercover. The suspension system includes a trailing arm, and a torsion beam extending along a vehicle width direction. The first undercover is disposed on a front side of the torsion beam in a vehicle front-rear direction. The second undercover is disposed on a rear side of the torsion beam. The first undercover is formed with a rear edge part at a rear edge extending toward the torsion beam along the vehicle front-rear direction. The second undercover includes a front end part at a front end. In a stationary state of a vehicle, an imaginary plane formed by connecting lower surfaces of the rear edge part of the first undercover and the front end part of the second undercover is formed at a position lower than the torsion beam in a vehicle up-down direction.

Abstract: A vehicle control system capable of improving aerodynamic performance of a vehicle is provided. The vehicle control system includes: a diffuser device installed on a rear bumper of a vehicle and configured to be movable between a storing position stored in the rear bumper and an extending position protruding from the rear bumper toward the rear of the vehicle; a natural wind detecting device installed on the vehicle to detect a direction of the natural wind relative to the vehicle; and a control device arranged on the vehicle and controlling movement of the diffuser device in response to the direction of the natural wind.

Abstract: A vehicle control system includes a diffuser device disposed on a rear bumper of a vehicle and configured to be movable between a first storage position stored in the rear bumper and a first unfolded position protruding from the rear bumper toward a rear of the vehicle, a spoiler device disposed on a roof plate of the vehicle and configured to be movable between a second storage position stored in the roof plate and a second unfolded position protruding from the roof plate toward the rear of the vehicle, a natural wind detection device disposed on the vehicle to detect a direction of natural wind relative to the vehicle, and a control device disposed on the vehicle and controlling the diffuser device and the spoiler device to move independently in response to the direction of the natural wind.

Abstract: Disclosed is a vehicle control system that may improve the aerodynamic performance of the vehicle. The vehicle control systems includes: a pair of left and right fairing devices, which are disposed in front of a pair of left and right wheels of the vehicle, and are each movable between a first storage position under the vehicle and a first deployment position protruding from the first storage position toward the lower part of the vehicle; a natural wind detection device disposed on the vehicle to detect the direction of the natural wind relative to the vehicle; and a control device disposed on the vehicle and controlling a pair of left and right fairing devices to move independently in response to the direction of the natural wind.

Abstract: Defect resistant designs for location-sensitive neural network processor arrays are provided. In various embodiments, plurality of neural network processor cores are arrayed in a grid. The grid has a plurality of rows and a plurality of columns. A network interconnects at least those of the plurality of neural network processor cores that are adjacent within the grid. The network is adapted to bypass a defective core of the plurality of neural network processor cores by providing a connection between two non-adjacent rows or columns of the grid, and transparently routing messages between the two non-adjacent rows or columns, past the defective core.

Abstract: Hardware neural network processors, are provided. A neural core includes a weight memory, an activation memory, a vector-matrix multiplier, and a vector processor. The vector-matrix multiplier is adapted to receive a weight matrix from the weight memory, receive an activation vector from the activation memory, and compute a vector-matrix multiplication of the weight matrix and the activation vector. The vector processor is adapted to receive one or more input vector from one or more vector source and perform one or more vector functions on the one or more input vector to yield an output vector. In some embodiments a programmable controller is adapted to configure and operate the neural core.

Abstract: Neural network processing hardware using parallel computational architectures with reconfigurable core-level and vector-level parallelism is provided. In various embodiments, a neural network model memory is adapted to store a neural network model comprising a plurality of layers. Each layer has at least one dimension and comprises a plurality of synaptic weights. A plurality of neural cores is provided. Each neural core includes a computation unit and an activation memory. The computation unit is adapted to apply a plurality of synaptic weights to a plurality of input activations to produce a plurality of output activations. The computation unit has a plurality of vector units. The activation memory is adapted to store the input activations and the output activations. The system is adapted to partition the plurality of cores into a plurality of partitions based on dimensions of the layer and the vector units.

Abstract: An object of the present invention is to provide a catalyst composition that partially oxidizes a hydrocarbon to produce hydrogen and carbon monoxide, the catalytic activity of which is unlikely to deteriorate even when the catalyst composition is exposed to a high temperature, and the present invention provides a catalyst composition that partially oxidizes a hydrocarbon to produce hydrogen and carbon monoxide, including: a carrier that contains ?-alumina; and a supported components that are supported on the carrier, wherein the supported components includes at least one platinum group element, a Ce oxide, and a Zr oxide.