Patents by Inventor Jun Tsukano

Jun Tsukano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11448914
    Abstract: A method of manufacturing an electronic module that comprises preparing an electronic device in which a first substrate and a second substrate have been joined and coupling the electronic device to a package member. The first substrate includes a front surface, a back surface on an opposite side of the front surface, and a first side surface between an edge portion of the front surface and an edge portion of the back surface. The package member includes a first portion that includes an opening and a second portion that is arranged at a position which does not overlap the opening. The coupling includes bringing the first side surface into contact with the second portion in a state in which the second substrate is positioned between the first portion and the first substrate, and fixing the package member and the electronic device.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: September 20, 2022
    Assignee: Canon Kabushiki Kaisha
    Inventor: Jun Tsukano
  • Publication number: 20210132431
    Abstract: A method of manufacturing an electronic module that comprises preparing an electronic device in which a first substrate and a second substrate have been joined and coupling the electronic device to a package member. The first substrate includes a front surface, a back surface on an opposite side of the front surface, and a first side surface between an edge portion of the front surface and an edge portion of the back surface. The package member includes a first portion that includes an opening and a second portion that is arranged at a position which does not overlap the opening. The coupling includes bringing the first side surface into contact with the second portion in a state in which the second substrate is positioned between the first portion and the first substrate, and fixing the package member and the electronic device.
    Type: Application
    Filed: October 20, 2020
    Publication date: May 6, 2021
    Inventor: Jun Tsukano
  • Publication number: 20200296271
    Abstract: An electronic component comprising: an electronic substrate that includes an electronic element and a first connection terminal a package member that is disposed on the electronic substrate; and a circuit member that includes a second connection terminal, wherein the circuit member is disposed between the package member and the electronic substrate, and extends from the position between the package member and the electronic substrate outward beyond the edge of the electronic substrate; the electronic component includes a connecting member that is disposed between the circuit member and the electronic substrate, and electrically connects the second connection terminal and the first connection terminal, an adhesive member that is disposed between the circuit member and the package member, and joins the circuit member to the package member; the connecting member, the circuit member, and the adhesive member are located between the package member and the electronic substrate.
    Type: Application
    Filed: March 5, 2020
    Publication date: September 17, 2020
    Inventor: Jun Tsukano
  • Patent number: 8389414
    Abstract: A wiring board has an insulating layer, a plurality of wiring layers formed in such a way as to be insulated from each other by the insulating layer, and a plurality of vias formed in the insulating layer to connect the wiring layers. Of the wiring layers, a surface wiring layer formed in one surface of the insulating layer include a first metal film exposed from the one surface and a second metal film embedded in the insulating layer and stacked on the first metal film. Edges of the first metal film project from edges of the second metal film in the direction in which the second metal film spreads. By designing the shape of the wiring layers embedded in the insulating layer in this manner, it is possible to obtain a highly reliable wiring board that can be effectively prevented from side etching in the manufacturing process and can adapt to miniaturization and highly dense packaging of wires.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: March 5, 2013
    Assignees: NEC Corporation, Renesas Electronics Corporation
    Inventors: Katsumi Kikuchi, Shintaro Yamamichi, Hideya Murai, Takuo Funaya, Kentaro Mori, Takehiko Maeda, Hirokazu Honda, Kenta Ogawa, Jun Tsukano
  • Patent number: 8304918
    Abstract: An electronic device is disclosed which can suppress the formation of voids in a region below an overhanging portion of a first semiconductor device overhanging a support member. The support member is disposed over a package substrate. The first semiconductor device is disposed over the support member and, when seen in plan, at least a part of the first semiconductor device overhangs the support member. A first resin layer fills up a space below the first semiconductor device in at least a part of the overhanging portion of the first semiconductor device around the support member. The first resin layer is in contact with the support member. A second resin layer seals the first semiconductor device and the support member.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: November 6, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Jun Tsukano
  • Publication number: 20110163458
    Abstract: An electronic device is disclosed which can suppress the formation of voids in a region below an overhanging portion of a first semiconductor device overhanging a support member. The support member is disposed over a package substrate. The first semiconductor device is disposed over the support member and, when seen in plan, at least a part of the first semiconductor device overhangs the support member. A first resin layer fills up a space below the first semiconductor device in at least a part of the overhanging portion of the first semiconductor device around the support member. The first resin layer is in contact with the support member. A second resin layer seals the first semiconductor device and the support member.
    Type: Application
    Filed: January 5, 2011
    Publication date: July 7, 2011
    Applicant: Renesas Electronics Corporation
    Inventor: Jun Tsukano
  • Publication number: 20110136298
    Abstract: A wiring board has an insulating layer, a plurality of wiring layers formed in such a way as to be insulated from each other by the insulating layer, and a plurality of vias formed in the insulating layer to connect the wiring layers. Of the wiring layers, a surface wiring layer formed in one surface of the insulating layer include a first metal film exposed from the one surface and a second metal film embedded in the insulating layer and stacked on the first metal film. Edges of the first metal film project from edges of the second metal film in the direction in which the second metal film spreads. By designing the shape of the wiring layers embedded in the insulating layer in this manner, it is possible to obtain a highly reliable wiring board that can be effectively prevented from side etching in the manufacturing process and can adapt to miniaturization and highly dense packaging of wires.
    Type: Application
    Filed: February 14, 2011
    Publication date: June 9, 2011
    Applicants: NEC CORPORATION, RENESAS ELECTRONICS CORPORATION
    Inventors: Katsumi KIKUCHI, Shintaro YAMAMICHI, Hideya MURAI, Takuo FUNAYA, Kentaro MORI, Takehiko MAEDA, Hirokazu HONDA, Kenta OGAWA, Jun TSUKANO
  • Patent number: 7911038
    Abstract: A wiring board has an insulating layer, a plurality of wiring layers formed in such a way as to be insulated from each other by the insulating layer, and a plurality of vias formed in the insulating layer to connect the wiring layers. Of the wiring layers, a surface wiring layer formed in one surface of the insulating layer include a first metal film exposed from the one surface and a second metal film embedded in the insulating layer and stacked on the first metal film. Edges of the first metal film project from edges of the second metal film in the direction in which the second metal film spreads. By designing the shape of the wiring layers embedded in the insulating layer in this manner, it is possible to obtain a highly reliable wiring board that can be effectively prevented from side etching in the manufacturing process and can adapt to miniaturization and highly dense packaging of wires.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: March 22, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Katsumi Kikuchi, Shintaro Yamamichi, Hideya Murai, Takuo Funaya, Kentaro Mori, Takehiko Maeda, Hirokazu Honda, Kenta Ogawa, Jun Tsukano
  • Patent number: 7888809
    Abstract: A semiconductor device including a substrate, a semiconductor chip mounted on the substrate, and an encapsulation resin encapsulating the semiconductor chip, wherein the encapsulation resin contains a first resin region composed of a first resin composition, a second resin region composed of a second resin composition, and a mixed layer formed between the first resin region and the second resin region so as to have the first resin composition and the second resin composition mixed therein is provided.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: February 15, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Yuichi Miyagawa, Takamitsu Noda, Hiroyasu Miyamoto, Jun Tsukano
  • Patent number: 7838779
    Abstract: A wiring board in which lower-layer wiring composed of a wiring body and an etching barrier layer is formed in a concave portion formed on one face of a board-insulating film, upper-layer wiring is formed on the other face of the board-insulating film, and the upper-layer wiring and the wiring body of the lower-layer wiring are connected to each other through a via hole formed in the board-insulating film. The via hole is barrel-shaped, bell-shaped, or bellows-shaped.
    Type: Grant
    Filed: June 15, 2006
    Date of Patent: November 23, 2010
    Assignees: NEC Corporation, NEC Electronics Corporation
    Inventors: Shintaro Yamamichi, Katsumi Kikuchi, Hideya Murai, Takuo Funaya, Takehiko Maeda, Kenta Ogawa, Jun Tsukano, Hirokazu Honda
  • Publication number: 20100232127
    Abstract: A wiring board composite body includes a supporting substrate, and wiring boards formed on each of the upper and the lower surfaces of the supporting substrate. The supporting substrate includes a supporting body, and a metal body arranged on each of the upper and the lower surfaces of the supporting body. The wiring board comprises at least an insulation layer insulating upper and lower wirings, and a via connecting the upper and the lower wirings. The wiring board mounted on the metal body constitutes a wiring board with the metal body. Thus, the supporting body supporting the metal body is effectively used in a process of forming the wiring board on the metal body, and the wiring board composite body, which has advantageous structural and production characteristics, is provided. A semiconductor device and a method for manufacturing such wiring board composite body and the semiconductor device are also provided.
    Type: Application
    Filed: September 4, 2007
    Publication date: September 16, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Kentaro Mori, Shintaro Yamamichi, Katsumi Kikuchi, Hideya Murai, Takuo Funaya, Takehiko Maeda, Hirokazu Honda, Kenta Ogawa, Jun Tsukano
  • Publication number: 20100176517
    Abstract: Differences in contraction forces of a sealing resin can be alleviated and strain on a package can be reduced even when electronic components are unevenly positioned on a substrate. An electronic device (100) includes a substrate 102, electronic components (104, 108) mounted on one face of the substrate 102, and a sealing resin 118 formed on the one face of the substrate 102 and which seals the electronic components. The sealing resin 118 includes a first resin region 120 made up of a first resin composition and a second resin region 122 made up of a second resin composition, and is formed so as to have, as seen in planar view, a region in which only the first resin region 120 exists and a region in which only the second resin region 122 exists.
    Type: Application
    Filed: January 6, 2010
    Publication date: July 15, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Yuichi Miyagawa, Jun Tsukano, Kenji Furuya, Takamitsu Noda, Hiroyasu Miyamoto
  • Patent number: 7745736
    Abstract: An interconnecting substrate is provided with a base insulating film having a sunken section in a bottom surface thereof, a first interconnection provided in the sunken section, a via hole formed in the base insulating film, and a second interconnection which is connected to the first interconnection via a conductor within the via hole and is formed on a top surface of the base insulating film, wherein the interconnecting substrate includes a first interconnection pattern formed of the first interconnection which includes at least a linear pattern which extends along a second direction orthogonal to a first direction, and a warpage-controlling pattern which is provided in the sunken section in the bottom surface of the base insulating film and is formed in such a manner as to suppress a warpage of the interconnecting substrate toward a bottom side on both sides of the first direction.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: June 29, 2010
    Assignees: NEC Electronics Corporation, NEC Corporation
    Inventors: Kenta Ogawa, Jun Tsukano, Takehiko Maeda, Tadanori Shimoto, Shintaro Yamamichi, Kazuhiro Baba
  • Publication number: 20100102461
    Abstract: A semiconductor device including a substrate, a semiconductor chip mounted on the substrate, and an encapsulation resin encapsulating the semiconductor chip, wherein the encapsulation resin contains a first resin region composed of a first resin composition, a second resin region composed of a second resin composition, and a mixed layer formed between the first resin region and the second resin region so as to have the first resin composition and the second resin composition mixed therein is provided.
    Type: Application
    Filed: October 22, 2009
    Publication date: April 29, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Yuichi Miyagawa, Takamitsu Noda, Hiroyasu Miyamoto, Jun Tsukano
  • Patent number: 7701726
    Abstract: A wiring substrate includes a base insulating film, a first interconnection formed on a top surface side of the base insulating film, a via conductor provided in a via hole formed in the base insulating film, and a second interconnection provided on a bottom surface side of the base insulating film, the second interconnection being connected to the first interconnection via the via conductor. The wiring substrate includes divided-substrate-unit regions, in each of which the first interconnection, the via conductor, and the second interconnection are formed.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: April 20, 2010
    Assignees: NEC Electronics Corporation, NEC Corporation
    Inventors: Jun Tsukano, Kenta Ogawa, Takehiko Maeda, Shintaro Yamamichi, Katsumi Kikuchi
  • Patent number: 7674989
    Abstract: A wiring board for mounting a semiconductor element or electronic component having a plurality of wiring layers, an insulating layer provided between these wiring layers, and a via which is provided to the insulating layer and which electrically connects the wiring layers. In this wiring board, the cross-sectional shape of the via in the plane parallel to the wiring layers is obtained by the partial overlapping of a plurality of similar shapes (circles). Stable operation can be obtained in a semiconductor element by minimizing obstacles to increased density, effectively increasing the cross-sectional area of the via, and preventing the wiring resistance from increasing by making the cross-sectional shape of the via into a shape obtained by the partial overlapping of a plurality of similar shapes.
    Type: Grant
    Filed: June 9, 2006
    Date of Patent: March 9, 2010
    Assignees: NEC Electronics Corporation, NEC Corporation
    Inventors: Katsumi Kikuchi, Shintaro Yamamichi, Hideya Murai, Takuo Funaya, Takehiko Maeda, Hirokazu Honda, Kenta Ogawa, Jun Tsukano
  • Patent number: 7649749
    Abstract: A wiring substrate includes a base insulating film, a first interconnection formed on a top surface side of the base insulating film, a via conductor provided in a via formed in the base insulating film, and a second interconnection provided on a bottom surface side of the base insulating film. The second interconnection is connected to the first interconnection via the via. The wiring substrate includes divided-substrate-unit regions, in each of which the first interconnection, the via, and the second interconnection are formed. The wiring substrate includes a warpage-controlling pattern on the base insulating film, with a warped shape such that when the wiring substrate rests on a horizontal plate, at least a central part of a plane surface of the substrate contacts the horizontal plate, with both ends of the side raised.
    Type: Grant
    Filed: July 9, 2007
    Date of Patent: January 19, 2010
    Assignees: NEC Electronics Corporation, NEC Corporation
    Inventors: Jun Tsukano, Kenta Ogawa, Takehiko Maeda, Shintaro Yamamichi, Katsumi Kikuchi
  • Publication number: 20090315190
    Abstract: A wiring board has an insulating layer, a plurality of wiring layers formed in such a way as to be insulated from each other by the insulating layer, and a plurality of vias formed in the insulating layer to connect the wiring layers. Of the wiring layers, a surface wiring layer formed in one surface of the insulating layer include a first metal film exposed from the one surface and a second metal film embedded in the insulating layer and stacked on the first metal film. Edges of the first metal film project from edges of the second metal film in the direction in which the second metal film spreads. By designing the shape of the wiring layers embedded in the insulating layer in this manner, it is possible to obtain a highly reliable wiring board that can be effectively prevented from side etching in the manufacturing process and can adapt to miniaturization and highly dense packaging of wires.
    Type: Application
    Filed: June 29, 2007
    Publication date: December 24, 2009
    Applicant: NEC CORPORATION
    Inventors: Katsumi Kikuchi, Shintaro Yamamichi, Hideya Murai, Takuo Funaya, Kentaro Mori, Takehiko Maeda, Hirokazu Honda, Kenta Ogawa, Jun Tsukano
  • Publication number: 20090137085
    Abstract: A wiring substrate includes a base insulating film, a first interconnection formed on a top surface side of the base insulating film, a via conductor provided in a via hole formed in the base insulating film, and a second interconnection provided on a bottom surface side of the base insulating film, the second interconnection being connected to the first interconnection via the via conductor. The wiring substrate includes divided-substrate-unit regions, in each of which the first interconnection, the via conductor, and the second interconnection are formed. The wiring substrate includes a warpage-controlling pattern on the base insulating film, and has a warped shape such that when the wiring substrate is left at rest on a horizontal plate, at least a central part of each side of a plane surface of the substrate contacts the horizontal plate, with both ends of the side raised, where each of the sides extends along a second direction perpendicular to a first direction in the plane surface of the substrate.
    Type: Application
    Filed: December 19, 2008
    Publication date: May 28, 2009
    Applicants: NEC ELECTRONICS CORPORATION, NEC CORPORATION
    Inventors: Jun TSUKANO, Kenta Ogawa, Takehiko Maeda, Shintaro Yamamichi, Katsumi Kikuchi
  • Publication number: 20080012140
    Abstract: A wiring substrate includes a base insulating film, a first interconnection formed on a top surface side of the base insulating film, a via conductor provided in a via hole formed in the base insulating film, and a second interconnection provided on a bottom surface side of the base insulating film, the second interconnection being connected to the first interconnection via the via conductor. The wiring substrate includes divided-substrate-unit regions, in each of which the first interconnection, the via conductor, and the second interconnection are formed. The wiring substrate includes a warpage-controlling pattern on the base insulating film, and has a warped shape such that when the wiring substrate is left at rest on a horizontal plate, at least a central part of each side of a plane surface of the substrate contacts the horizontal plate, with both ends of the side raised, where each of the sides extends along a second direction perpendicular to a first direction in the plane surface of the substrate.
    Type: Application
    Filed: July 9, 2007
    Publication date: January 17, 2008
    Applicants: NEC ELECTRONICS CORPORATION, NEC CORPORATION
    Inventors: Jun Tsukano, Kenta Ogawa, Takehiko Maeda, Shintaro Yamamichi, Katsumi Kikuchi