Patents by Inventor Jun Tsukano
Jun Tsukano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12292657Abstract: A manufacturing method of an electronic component includes preparing a first structure in which a first electrode is arranged on a first main surface of a first substrate, preparing a second structure in which a second electrode is arranged on a first main surface of a second substrate, and curing a bonding member while making the first main surface of the first substrate and the first main surface of the second substrate face each other via the bonding member and applying a force to the first structure and the second structure so as to pressurize the bonding member. At least one of the first electrode and the second electrode includes a window portion. In the curing, the bonding member is cured by irradiating the bonding member with light through the window portion.Type: GrantFiled: May 16, 2024Date of Patent: May 6, 2025Assignee: Canon Kabushiki KaishaInventor: Jun Tsukano
-
Publication number: 20240306306Abstract: A manufacturing method of an electronic component includes preparing a first structure in which a first electrode is arranged on a first main surface of a first substrate, preparing a second structure in which a second electrode is arranged on a first main surface of a second substrate, and curing a bonding member while making the first main surface of the first substrate and the first main surface of the second substrate face each other via the bonding member and applying a force to the first structure and the second structure so as to pressurize the bonding member. At least one of the first electrode and the second electrode includes a window portion. In the curing, the bonding member is cured by irradiating the bonding member with light through the window portion.Type: ApplicationFiled: May 16, 2024Publication date: September 12, 2024Inventor: JUN TSUKANO
-
Publication number: 20240107670Abstract: An electronic component includes first and second electrodes, first and second substrates having first and second principal surfaces, respectively, and a connection member to connect the first and second electrodes, wherein the first and second electrodes are arranged on the first and second principal surfaces, respectively, a height of the connection member is greater than those of the first and second electrodes in the direction perpendicular to the first principal surface, a distance between a portion of the first principal surface not in contact with the first electrode and a portion of the second principal surface not in contact with the second electrode is shorter than a distance between a portion of the first principal surface in contact with the first electrode and a portion of the second principal surface in contact with the second electrode, and an intermediary body is arranged between the second electrode and the connection member.Type: ApplicationFiled: September 26, 2023Publication date: March 28, 2024Inventor: JUN TSUKANO
-
Patent number: 11765448Abstract: An electronic component comprising: an electronic substrate that includes an electronic element and a first connection terminal a package member that is disposed on the electronic substrate; and a circuit member that includes a second connection terminal, wherein the circuit member is disposed between the package member and the electronic substrate, and extends from the position between the package member and the electronic substrate outward beyond the edge of the electronic substrate; the electronic component includes a connecting member that is disposed between the circuit member and the electronic substrate, and electrically connects the second connection terminal and the first connection terminal, an adhesive member that is disposed between the circuit member and the package member, and joins the circuit member to the package member; the connecting member, the circuit member, and the adhesive member are located between the package member and the electronic substrate.Type: GrantFiled: October 21, 2022Date of Patent: September 19, 2023Assignee: CANON KABUSHIKI KAISHAInventor: Jun Tsukano
-
Publication number: 20230247768Abstract: A manufacturing method of an electronic component includes preparing a first structure in which a first electrode is arranged on a first main surface of a first substrate, preparing a second structure in which a second electrode is arranged on a first main surface of a second substrate, and curing a bonding member while making the first main surface of the first substrate and the first main surface of the second substrate face each other via the bonding member and applying a force to the first structure and the second structure so as to pressurize the bonding member. At least one of the first electrode and the second electrode includes a window portion. In the curing, the bonding member is cured by irradiating the bonding member with light through the window portion.Type: ApplicationFiled: January 10, 2023Publication date: August 3, 2023Inventor: JUN TSUKANO
-
Publication number: 20230053757Abstract: An electronic component comprising: an electronic substrate that includes an electronic element and a first connection terminal a package member that is disposed on the electronic substrate; and a circuit member that includes a second connection terminal, wherein the circuit member is disposed between the package member and the electronic substrate, and extends from the position between the package member and the electronic substrate outward beyond the edge of the electronic substrate; the electronic component includes a connecting member that is disposed between the circuit member and the electronic substrate, and electrically connects the second connection terminal and the first connection terminal, an adhesive member that is disposed between the circuit member and the package member, and joins the circuit member to the package member; the connecting member, the circuit member, and the adhesive member are located between the package member and the electronic substrate.Type: ApplicationFiled: October 21, 2022Publication date: February 23, 2023Inventor: Jun Tsukano
-
Patent number: 11528392Abstract: An electronic component comprising: an electronic substrate that includes an electronic element and a first connection terminal a package member that is disposed on the electronic substrate; and a circuit member that includes a second connection terminal, wherein the circuit member is disposed between the package member and the electronic substrate, and extends from the position between the package member and the electronic substrate outward beyond the edge of the electronic substrate; the electronic component includes a connecting member that is disposed between the circuit member and the electronic substrate, and electrically connects the second connection terminal and the first connection terminal, an adhesive member that is disposed between the circuit member and the package member, and joins the circuit member to the package member; the connecting member, the circuit member, and the adhesive member are located between the package member and the electronic substrate.Type: GrantFiled: March 5, 2020Date of Patent: December 13, 2022Assignee: CANON KABUSHIKI KAISHAInventor: Jun Tsukano
-
Patent number: 11448914Abstract: A method of manufacturing an electronic module that comprises preparing an electronic device in which a first substrate and a second substrate have been joined and coupling the electronic device to a package member. The first substrate includes a front surface, a back surface on an opposite side of the front surface, and a first side surface between an edge portion of the front surface and an edge portion of the back surface. The package member includes a first portion that includes an opening and a second portion that is arranged at a position which does not overlap the opening. The coupling includes bringing the first side surface into contact with the second portion in a state in which the second substrate is positioned between the first portion and the first substrate, and fixing the package member and the electronic device.Type: GrantFiled: October 20, 2020Date of Patent: September 20, 2022Assignee: Canon Kabushiki KaishaInventor: Jun Tsukano
-
Publication number: 20210132431Abstract: A method of manufacturing an electronic module that comprises preparing an electronic device in which a first substrate and a second substrate have been joined and coupling the electronic device to a package member. The first substrate includes a front surface, a back surface on an opposite side of the front surface, and a first side surface between an edge portion of the front surface and an edge portion of the back surface. The package member includes a first portion that includes an opening and a second portion that is arranged at a position which does not overlap the opening. The coupling includes bringing the first side surface into contact with the second portion in a state in which the second substrate is positioned between the first portion and the first substrate, and fixing the package member and the electronic device.Type: ApplicationFiled: October 20, 2020Publication date: May 6, 2021Inventor: Jun Tsukano
-
Publication number: 20200296271Abstract: An electronic component comprising: an electronic substrate that includes an electronic element and a first connection terminal a package member that is disposed on the electronic substrate; and a circuit member that includes a second connection terminal, wherein the circuit member is disposed between the package member and the electronic substrate, and extends from the position between the package member and the electronic substrate outward beyond the edge of the electronic substrate; the electronic component includes a connecting member that is disposed between the circuit member and the electronic substrate, and electrically connects the second connection terminal and the first connection terminal, an adhesive member that is disposed between the circuit member and the package member, and joins the circuit member to the package member; the connecting member, the circuit member, and the adhesive member are located between the package member and the electronic substrate.Type: ApplicationFiled: March 5, 2020Publication date: September 17, 2020Inventor: Jun Tsukano
-
Patent number: 8389414Abstract: A wiring board has an insulating layer, a plurality of wiring layers formed in such a way as to be insulated from each other by the insulating layer, and a plurality of vias formed in the insulating layer to connect the wiring layers. Of the wiring layers, a surface wiring layer formed in one surface of the insulating layer include a first metal film exposed from the one surface and a second metal film embedded in the insulating layer and stacked on the first metal film. Edges of the first metal film project from edges of the second metal film in the direction in which the second metal film spreads. By designing the shape of the wiring layers embedded in the insulating layer in this manner, it is possible to obtain a highly reliable wiring board that can be effectively prevented from side etching in the manufacturing process and can adapt to miniaturization and highly dense packaging of wires.Type: GrantFiled: February 14, 2011Date of Patent: March 5, 2013Assignees: NEC Corporation, Renesas Electronics CorporationInventors: Katsumi Kikuchi, Shintaro Yamamichi, Hideya Murai, Takuo Funaya, Kentaro Mori, Takehiko Maeda, Hirokazu Honda, Kenta Ogawa, Jun Tsukano
-
Patent number: 8304918Abstract: An electronic device is disclosed which can suppress the formation of voids in a region below an overhanging portion of a first semiconductor device overhanging a support member. The support member is disposed over a package substrate. The first semiconductor device is disposed over the support member and, when seen in plan, at least a part of the first semiconductor device overhangs the support member. A first resin layer fills up a space below the first semiconductor device in at least a part of the overhanging portion of the first semiconductor device around the support member. The first resin layer is in contact with the support member. A second resin layer seals the first semiconductor device and the support member.Type: GrantFiled: January 5, 2011Date of Patent: November 6, 2012Assignee: Renesas Electronics CorporationInventor: Jun Tsukano
-
Publication number: 20110163458Abstract: An electronic device is disclosed which can suppress the formation of voids in a region below an overhanging portion of a first semiconductor device overhanging a support member. The support member is disposed over a package substrate. The first semiconductor device is disposed over the support member and, when seen in plan, at least a part of the first semiconductor device overhangs the support member. A first resin layer fills up a space below the first semiconductor device in at least a part of the overhanging portion of the first semiconductor device around the support member. The first resin layer is in contact with the support member. A second resin layer seals the first semiconductor device and the support member.Type: ApplicationFiled: January 5, 2011Publication date: July 7, 2011Applicant: Renesas Electronics CorporationInventor: Jun Tsukano
-
Publication number: 20110136298Abstract: A wiring board has an insulating layer, a plurality of wiring layers formed in such a way as to be insulated from each other by the insulating layer, and a plurality of vias formed in the insulating layer to connect the wiring layers. Of the wiring layers, a surface wiring layer formed in one surface of the insulating layer include a first metal film exposed from the one surface and a second metal film embedded in the insulating layer and stacked on the first metal film. Edges of the first metal film project from edges of the second metal film in the direction in which the second metal film spreads. By designing the shape of the wiring layers embedded in the insulating layer in this manner, it is possible to obtain a highly reliable wiring board that can be effectively prevented from side etching in the manufacturing process and can adapt to miniaturization and highly dense packaging of wires.Type: ApplicationFiled: February 14, 2011Publication date: June 9, 2011Applicants: NEC CORPORATION, RENESAS ELECTRONICS CORPORATIONInventors: Katsumi KIKUCHI, Shintaro YAMAMICHI, Hideya MURAI, Takuo FUNAYA, Kentaro MORI, Takehiko MAEDA, Hirokazu HONDA, Kenta OGAWA, Jun TSUKANO
-
Patent number: 7911038Abstract: A wiring board has an insulating layer, a plurality of wiring layers formed in such a way as to be insulated from each other by the insulating layer, and a plurality of vias formed in the insulating layer to connect the wiring layers. Of the wiring layers, a surface wiring layer formed in one surface of the insulating layer include a first metal film exposed from the one surface and a second metal film embedded in the insulating layer and stacked on the first metal film. Edges of the first metal film project from edges of the second metal film in the direction in which the second metal film spreads. By designing the shape of the wiring layers embedded in the insulating layer in this manner, it is possible to obtain a highly reliable wiring board that can be effectively prevented from side etching in the manufacturing process and can adapt to miniaturization and highly dense packaging of wires.Type: GrantFiled: June 29, 2007Date of Patent: March 22, 2011Assignee: Renesas Electronics CorporationInventors: Katsumi Kikuchi, Shintaro Yamamichi, Hideya Murai, Takuo Funaya, Kentaro Mori, Takehiko Maeda, Hirokazu Honda, Kenta Ogawa, Jun Tsukano
-
Patent number: 7888809Abstract: A semiconductor device including a substrate, a semiconductor chip mounted on the substrate, and an encapsulation resin encapsulating the semiconductor chip, wherein the encapsulation resin contains a first resin region composed of a first resin composition, a second resin region composed of a second resin composition, and a mixed layer formed between the first resin region and the second resin region so as to have the first resin composition and the second resin composition mixed therein is provided.Type: GrantFiled: October 22, 2009Date of Patent: February 15, 2011Assignee: Renesas Electronics CorporationInventors: Yuichi Miyagawa, Takamitsu Noda, Hiroyasu Miyamoto, Jun Tsukano
-
Patent number: 7838779Abstract: A wiring board in which lower-layer wiring composed of a wiring body and an etching barrier layer is formed in a concave portion formed on one face of a board-insulating film, upper-layer wiring is formed on the other face of the board-insulating film, and the upper-layer wiring and the wiring body of the lower-layer wiring are connected to each other through a via hole formed in the board-insulating film. The via hole is barrel-shaped, bell-shaped, or bellows-shaped.Type: GrantFiled: June 15, 2006Date of Patent: November 23, 2010Assignees: NEC Corporation, NEC Electronics CorporationInventors: Shintaro Yamamichi, Katsumi Kikuchi, Hideya Murai, Takuo Funaya, Takehiko Maeda, Kenta Ogawa, Jun Tsukano, Hirokazu Honda
-
Publication number: 20100232127Abstract: A wiring board composite body includes a supporting substrate, and wiring boards formed on each of the upper and the lower surfaces of the supporting substrate. The supporting substrate includes a supporting body, and a metal body arranged on each of the upper and the lower surfaces of the supporting body. The wiring board comprises at least an insulation layer insulating upper and lower wirings, and a via connecting the upper and the lower wirings. The wiring board mounted on the metal body constitutes a wiring board with the metal body. Thus, the supporting body supporting the metal body is effectively used in a process of forming the wiring board on the metal body, and the wiring board composite body, which has advantageous structural and production characteristics, is provided. A semiconductor device and a method for manufacturing such wiring board composite body and the semiconductor device are also provided.Type: ApplicationFiled: September 4, 2007Publication date: September 16, 2010Applicant: NEC ELECTRONICS CORPORATIONInventors: Kentaro Mori, Shintaro Yamamichi, Katsumi Kikuchi, Hideya Murai, Takuo Funaya, Takehiko Maeda, Hirokazu Honda, Kenta Ogawa, Jun Tsukano
-
Publication number: 20100176517Abstract: Differences in contraction forces of a sealing resin can be alleviated and strain on a package can be reduced even when electronic components are unevenly positioned on a substrate. An electronic device (100) includes a substrate 102, electronic components (104, 108) mounted on one face of the substrate 102, and a sealing resin 118 formed on the one face of the substrate 102 and which seals the electronic components. The sealing resin 118 includes a first resin region 120 made up of a first resin composition and a second resin region 122 made up of a second resin composition, and is formed so as to have, as seen in planar view, a region in which only the first resin region 120 exists and a region in which only the second resin region 122 exists.Type: ApplicationFiled: January 6, 2010Publication date: July 15, 2010Applicant: NEC ELECTRONICS CORPORATIONInventors: Yuichi Miyagawa, Jun Tsukano, Kenji Furuya, Takamitsu Noda, Hiroyasu Miyamoto
-
Patent number: 7745736Abstract: An interconnecting substrate is provided with a base insulating film having a sunken section in a bottom surface thereof, a first interconnection provided in the sunken section, a via hole formed in the base insulating film, and a second interconnection which is connected to the first interconnection via a conductor within the via hole and is formed on a top surface of the base insulating film, wherein the interconnecting substrate includes a first interconnection pattern formed of the first interconnection which includes at least a linear pattern which extends along a second direction orthogonal to a first direction, and a warpage-controlling pattern which is provided in the sunken section in the bottom surface of the base insulating film and is formed in such a manner as to suppress a warpage of the interconnecting substrate toward a bottom side on both sides of the first direction.Type: GrantFiled: January 30, 2006Date of Patent: June 29, 2010Assignees: NEC Electronics Corporation, NEC CorporationInventors: Kenta Ogawa, Jun Tsukano, Takehiko Maeda, Tadanori Shimoto, Shintaro Yamamichi, Kazuhiro Baba