Patents by Inventor Jun Ueda

Jun Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070053167
    Abstract: An electronic circuit module includes (i) a semiconductor integrated circuit component which is a transistor integrated circuit formed on a semiconductor substrate, (ii) a passive element component constituting a peripheral circuit of the semiconductor integrated circuit component, and (iii) first and second circuit substrates each of which has a component mounting surface on which at least one of the semiconductor integrated circuit component and the passive element component. The respective component mounting surfaces of the first and second circuit substrate face one another. The first circuit substrate functions as one outer wall of a housing, where the electronic circuit module contacts an external circuit substrate on which the electronic circuit module is mounted. The second circuit substrate functions as the other outer wall of the housing of the module.
    Type: Application
    Filed: September 8, 2006
    Publication date: March 8, 2007
    Applicant: Sharp Kabushiki Kaisha
    Inventor: Jun Ueda
  • Publication number: 20060066572
    Abstract: A pointing device includes a sensor obtaining image information, and an image producing unit producing a comparison image at predetermined time intervals by lowering a spatial resolution of an image based on the image information obtained by the sensor and increasing a density resolution of the image based on the image information. The device arithmetically obtains a correlation value indicating a correlation between a predetermined region in a first comparison image among the plurality of comparison images produced by the image producing unit and a predetermined region in a second comparison image produced after the first comparison image.
    Type: Application
    Filed: September 27, 2005
    Publication date: March 30, 2006
    Inventors: Manabu Yumoto, Takahiko Nakano, Takuji Urata, Sohichi Miyata, Jun Ueda, Tsukasa Ogasawara
  • Publication number: 20060012570
    Abstract: A pointing device that does not limit an operator by personal physical characteristics is structured as follows. An apparatus incorporating a pointing device includes a fingerprint sensor obtaining image information, a cover protecting a sensor surface, and a sensor presser arranged at a face of the cover on the sensor side so as to be in contact with the sensor surface. The shape of sensor presser obtained with sensor changes by the position on cover being pressed by a finger, and an input is performed based thereon.
    Type: Application
    Filed: June 8, 2005
    Publication date: January 19, 2006
    Applicants: Sharp Kabushiki Kaisha, National University Corporation Nara Institute of Science and Technology
    Inventors: Manabu Yumoto, Nobuhisa Tsuji, Sohichi Miyata, Jun Ueda, Tsukasa Ogasawara
  • Publication number: 20050219254
    Abstract: A drawing tool for drawing pattern parts with held attributes is provided. It draws pattern parts, based only on a desired pattern part being selected from a pattern part window, and the pattern part passing, along a route in which the pattern part moves with dragged onto a drawing canvas, through a desired attribute display region of attribute palettes for displaying its attributes given with respect to the pattern part, so that the attribute can be selected and set by the pattern part only passing, along the route in which an attribute of the pattern part drawn on the drawing canvas is dragged and dropped onto the drawing canvas, through the attribute display region for displaying the desired attribute; therefore, drawings can be performed by minimal operation.
    Type: Application
    Filed: March 5, 2003
    Publication date: October 6, 2005
    Inventor: Jun Ueda
  • Publication number: 20050102651
    Abstract: A programming tool has selection means for selecting a plurality of function blocks displayed in a library format, storage means for storing the function blocks selected through the selection means in the order as they are selected, and drawing means, as a plurality of function blocks selected through the selection means are confirmed, for drawing and display the confirmed function blocks in the order as they are selected.
    Type: Application
    Filed: March 29, 2001
    Publication date: May 12, 2005
    Inventor: Jun Ueda
  • Patent number: 4649414
    Abstract: In a planer type PNPN semiconductor switch having a MOS FET structure, a field plate electrode is embedded in an insulator covering a surface of a semiconductor substrate to overlie an interface between the semiconductor substrate and a P gate region for limiting an extention of a depletion layer from an anode region to a P gate region.
    Type: Grant
    Filed: September 18, 1985
    Date of Patent: March 10, 1987
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Jun Ueda, Hirokazu Tsukada, Yoichi Nanba
  • Patent number: 4582415
    Abstract: The gap between a magnetic sensor and a fitting member supporting the magnetic sensor and the surface of the magnetic sensor are coated with thin nonmagnetic coating materials having small surface friction to prevent the developer from being introduced into the gap and adhered therein. Smooth flow of the developer is maintained, and the stable and accurate detection of the condition or ratio of the developer is ensured.
    Type: Grant
    Filed: April 23, 1984
    Date of Patent: April 15, 1986
    Assignee: Mita Industrial Co., Ltd.
    Inventors: Keiichiro Hyodo, Hiroshi Ishida, Jun Ueda
  • Patent number: 4489340
    Abstract: A PNPN semiconductor switch including an N type semiconductor substrate, spaced apart first and second P type diffused regions formed on a surface of an N type substrate, spaced apart first and second N type diffused regions formed in the second P type diffused region, a first gate insulating layer formed on the surface of the second P type diffused region between the first and second N type diffused regions to cover portions thereof, a first gate electrode formed on the first gate insulating layer between the first and second N type diffused regions, a resistance region disposed on the first gate insulating layer, one end of the resistance region on the side opposite to the first gate electrode, a second gate insulating layer overlying the first gate electrode and the resistance region, a semiinsulating layer formed on the surface of the substrate except over the first and second P type diffused regions, an insulating layer overlying the semiinsulating layer, a P gate electrode electrically connected to the
    Type: Grant
    Filed: January 28, 1981
    Date of Patent: December 18, 1984
    Assignees: Nippon Telegraph & Telephone Public Corporation, Oki Electric Industry Co., Ltd.
    Inventors: Jun Ueda, Haruo Mori, Kazuo Hagimura, Hirokazu Tsukada, Kotaro Kato
  • Patent number: 4382691
    Abstract: In an analog electronic watch having a calendar display the power required during change of the calendar display, about 6 hours out of 24, is greater than at other times. In order to effect economy in power consumption, the pulse for driving the watch motor during the time other than the period in which the calendar display is being changed is only sufficient to drive the time indicating means. In case the motor fails to step when such pulse is applied, this is detected by a detecting circuit and a corrective drive pulse is applied to the motor so as to drive it.
    Type: Grant
    Filed: July 16, 1980
    Date of Patent: May 10, 1983
    Assignee: Kabushiki Kaisha Daini Seikosha
    Inventors: Masaharu Shida, Akira Torisawa, Jun Ueda, Masaaki Mandai, Katsuhiko Sato
  • Patent number: 4244000
    Abstract: A circuit for preventing a dV/dt erroneous operation of a PNPN semiconductor switch is replaced by a capacitance on the surface of a semiconductor substrate, a high resistance gate electrode. In other words, such a circuit is formed on the surface of the substrate by a slight modification of the basic design without decreasing the chip area and without isolating component elements.
    Type: Grant
    Filed: November 20, 1979
    Date of Patent: January 6, 1981
    Assignees: Nippon Telegraph and Telephone Public Corporation, Oki Electric Industry Company, Ltd.
    Inventors: Jun Ueda, Haruo Mori, Kazuo Hagimura, Kotaro Kato