Abstract: A method for programming at least one memory cell of a plurality of memory cells included in a non-volatile memory device, the at least one memory cell including a word line and a bit line, the method including: performing a first and second program and verify operation based on a first and second condition, respectively, wherein each program and verify operation includes generating a program voltage and a bit line voltage by a voltage generator included in the non-volatile memory device and providing the program voltage and the bit line voltage to the word line and the bit line, respectively, wherein voltage levels and voltage application times of each program voltage and bit line voltage correspond to the first condition or the second condition, respectively, wherein the first condition is different from the second condition.

Abstract: A memory device for improving the speed of a program operation and an operating method thereof is provided. The memory device includes a memory cell array including a plurality of memory cells, a voltage generator configured to generate voltages for one or more program operations and a verify operation performed on the plurality of memory cells, a control logic configured to perform a control operation on the plurality of memory cells so that a first program and a second program loop are performed, a second program operation being performed based on a compensation voltage level determined based on a result of the first verify operation, and a plurality of bit lines connected to the memory cell array, wherein the first verify operation includes first even sensing and second even sensing on even-numbered bit lines, and first odd sensing and second odd sensing on odd-numbered bit lines.

Abstract: Systems, methods, and machine-storage mediums for optimizing snapshot image processing are described. The system receives a first read request to read data from optimized snapshot information including snapshot information and cached snapshot information. The first read request includes a first offset identifying a first storage location and a first length. The snapshot information includes a full snapshot and at least one incremental snapshot. The system identifies a first portion of the data is stored in the snapshot information responsive to identifying the first portion of the data is not stored in the cache snapshot information. The system identifies a second portion of data is stored in the optimized snapshot information, reads the first portion of data and the second portion of data from the optimized snapshot information, and communicates the data, including the first and second portions of the data, to the job.

Abstract: Disclosed are an electrolyte for a lithium secondary battery, and a lithium secondary battery. The electrolyte for a lithium secondary battery includes a lithium salt; an organic solvent; and an additive, wherein the additive includes a compound represented by Formula 1. In Formula 1, R1 to R5 are as defined in the detailed description of the disclosure.

Abstract: The present disclosure relates to a method and apparatus for searching for a light-weight model through the replacement of a subnetwork of a trained neural network model. The method of searching for a light-weight model includes a preprocessing step of extracting a subnetwork from an original neural network model, constructing a mapping relation between the subnetwork and an alternative block corresponding to the subnetwork by extracting the alternative block from a pre-trained neural network model, and generating profiling information including performance information relating to the subnetwork and the alternative block, and a query processing step of receiving a query, extracting a constraint that is included in the query through query parsing, and generating the final model based on the constraint, the original neural network model, the alternative block, the mapping relation, and the profiling information.

Abstract: A negative electrode for a lithium metal battery, a lithium metal battery including the same, and a method of preparing the negative electrode are provided. The negative electrode includes a negative electrode current collector, and a protective layer disposed on the negative electrode current collector. The protective layer includes a first protective layer and a second protective layer disposed between the first protective layer and the negative electrode current collector. The first protective layer includes porous nanostructure particles, and the second protective layer includes polar inorganic particles.

Abstract: A motion processing method and apparatus are provided. The motion processing method includes obtaining a base-level motion by applying a linear Gaussian model to an input motion, obtaining a controllable motion displacement vector and a residual motion displacement vector by applying the linear Gaussian model to a displacement vector between the input motion and the base-level motion, and synthesizing an output motion based on the base-level motion and the controllable motion displacement vector.

Abstract: A display device includes a scan line extending in a first direction, a data line and a driving voltage line extending in a second direction crossing the first direction, a switching thin film transistor (“TFT”) connected to the scan line and the data line, a driving TFT connected to the switching TFT and including a driving semiconductor layer and a driving gate electrode, a storage capacitor connected to the driving TFT and including first and second storage capacitor plates, a node connection line between the data line and the driving voltage line and connected to the driving gate electrode, and a shielding portion between the data line and the node connection line.

Abstract: Each of a plurality of stages of a gate driving circuit includes a first node controller configured to control voltage levels of a first node and a second node, a second node controller configured to control a voltage level of a third node, and a first output unit configured to output the first voltage or the second voltage as a gate signal according to the voltage levels of the second node and the third node. The first node controller includes a single gate transistor having one gate and a dual gate transistor having a pair of gates disposed in different layers with a semiconductor disposed therebetween.

Abstract: Systems, apparatuses and methods may provide for developer stage technology that embeds binary code into an application binary file, wherein the binary code corresponds to vector functions and non-vector functions in statically typed source code, and generates intermediate representation (IR) data, wherein the intermediate representation data corresponds to the vector functions in the statically typed source code. Additionally, the developer stage technology embeds the IR data in the application binary file. Moreover, deployment stage technology may generate a first compilation output based on the application binary file and detect a capability change in an execution environment associated with the first compilation output. The deployment stage technology may also generate, in response to the detected capability change, a second compilation output based on the first compilation output.

Abstract: Provided is an accelerometer. The accelerometer includes a frame portion with an opening formed inside, a central portion disposed in the opening, a connecting portion disposed on an upper surface and a lower surface of the central portion and connecting the frame portion and the central portion, and a sensing portion that converts a sensed acceleration into an electrical signal, and the accelerometer senses an acceleration in a Z-axis direction penetrating an upper surface and a lower surface of the central portion, and reduces a sensing of an acceleration in an X-axis direction and a Y-axis direction crossing the Z-axis direction.