Abstract: A display device includes: a pixel defining layer defining openings arranged in first and second directions, the openings forming emission areas in which light emitting elements are disposed to emit light of different colors; a light blocking layer disposed on the pixel defining layer, and defining holes, each overlapping the opening and having a larger diameter than the opening; and color filters disposed on the light blocking layer to overlap the holes and overlap the emission areas. The opening has an opening interval, which is defined as a difference in diameter between the overlapping hole and the opening, in the openings, among homogeneous openings in which the light emitting elements for emitting light of the same color are disposed, the homogeneous openings adjacent in the first or second direction have different opening intervals, and among the homogeneous openings, openings having different opening intervals are at least three types.

Abstract: Provided is a flash memory integrated circuit with a compression codec. The flash memory integrated circuit may simultaneously include a memory block and a compression codec circuit. The compression codec circuit may compress input data. A controller circuit may store the compressed input data in at least one page that is included in the memory block. Through this, it is possible to enhance a usage efficiency of a flash memory.

Abstract: Provided is a flash memory integrated circuit with a compression codec. The flash memory integrated circuit may simultaneously include a memory block and a compression codec circuit. The compression codec circuit may compress input data. A controller circuit may store the compressed input data in at least one page that is included in the memory block. Through this, it is possible to enhance a usage efficiency of a flash memory.

Abstract: A semiconductor memory device is disclosed. The device comprises at least one data input/output reference signal input and output pin and a plurality of integrated circuits, each with a data input/output reference signal input and output pad connected to the data input/output reference signal input and output pin. Each integrated circuit further comprises a data input/output reference signal input and output buffer for buffering a data input/output reference signal input from the data input/output reference signal input and output pad when data is input. This buffer also buffers an internally generated data input/output reference signal, and outputs the buffered signal when data is output. The internally generated data input/output reference signal output can be disabled on each integrated circuit in response to a control signal, thus allowing a single one of the plurality of integrated circuits to be selected to generate the reference signal.

Abstract: Multi-chip memory devices include at least two integrated circuit memory chips, each of which includes corresponding address pads, data pads and control signal pads, and a common package that encapsulates the at least two integrated circuit memory chips, and that includes external terminals. An internal connection circuit in the common package is configured to connect at least one of the corresponding control signal pads of each of the integrated circuit memory chips to separate ones of the external terminals, to allow independent external control of each of the integrated circuit memory chips that are encapsulated in the common package. Multi-chip memory devices may be combined to form memory modules. The memory modules include a memory module substrate having first and second opposing surfaces. At least one multi-chip memory device, as described above, is provided on the first surface and on the second surface.

Abstract: A semiconductor memory device is disclosed. The device comprises at least one data input/output reference signal input and output pin and a plurality of integrated circuits, each with a data input/output reference signal input and output pad connected to the data input/output reference signal input and output pin. Each integrated circuit further comprises a data input/output reference signal input and output buffer for buffering a data input/output reference signal input from the data input/output reference signal input and output pad when data is input. This buffer also buffers an internally generated data input/output reference signal, and outputs the buffered signal when data is output. The internally generated data input/output reference signal output can be disabled on each integrated circuit in response to a control signal, thus allowing a single one of the plurality of integrated circuits to be selected to generate the reference signal.

Abstract: Dual-lead type substantially square semiconductor packages and dual in-line memory modules using them are disclosed. The conventional memory module is internationally standardized, so it is hard to increase memory density by adding current packages to the module. The substantially square semiconductor packages provide improved and smaller packages in which a package length and a pin pitch are reduced, so that the memory density is increased without modifying a module size. The length of the leads are preferably substantially equal.

Abstract: Multi-chip memory devices include at least two integrated circuit memory chips, each of which includes corresponding address pads, data pads and control signal pads, and a common package that encapsulates the at least two integrated circuit memory chips, and that includes external terminals. An internal connection circuit in the common package is configured to connect at least one of the corresponding control signal pads of each of the integrated circuit memory chips to separate ones of the external terminals, to allow independent external control of each of the integrated circuit memory chips that are encapsulated in the common package. Multi-chip memory devices may be combined to form memory modules. The memory modules include a memory module substrate having first and second opposing surfaces. At least one multi-chip memory device, as described above, is provided on the first surface and on the second surface.

Abstract: A memory module on a printed circuit board (PCB) has double density without increasing the area and height thereof. The memory module includes a first memory bank and a second memory bank that share data lines on the PCB. Each bank includes a group of packaged semiconductor memory devices. The memory module of the invention additionally includes a programmable logic device (PLD). The PLD outputs signals that selectively enable one of the first and second banks, in response to a bank select signal and control signals received from a memory controller. The package of the plurality of semiconductor memory devices is a shrink Thin Small Outline Package (sTSOP) or a chip size package (CSP) or plastic in which a length and a width are similar to each other.

Abstract: In the present invention, a semiconductor device includes a first insulation layer formed on a semiconductor substrate, an elevating pad formed on the first insulation layer, a second insulation layer covering the elevating pad, a plurality of fuses formed on the second insulation layer and over the elevating pad, a third insulation layer formed on the fuses, and an opening formed in a top portion of the third insulation layer and over the fuses. With this invention, the horizontal level of the fuses are elevated due to the existence of the elevating pad, which makes the distance between the fuse window and fuses be closer than that of the conventional and that reduces the step difference. Thus, a laser beam can reliably blow out all of the fuses reliably.

Abstract: Integrated circuit packages include an integrated circuit substrate having microelectronic devices therein and pads, wherein first ones of the pads are enabled to provide output data from the microelectronic devices, and wherein second ones of the pads are disabled to provide a reduced path width for the integrated circuit substrate. A packaging substrate includes terminals, a respective one of which is connected to a respective one of the pads, including the second ones of pads that are disabled to provide a reduced path width for the integrated circuit substrate. Accordingly, the same packaging substrates may be used with integrated circuit substrates having different path widths. In a preferred embodiment, the integrated circuit substrate includes a control circuit that disables the second ones of the pads to provide a reduced path width for the integrated circuit substrate.

Abstract: A semiconductor memory device is disclosed. The device can be controlled by a controller for another less integrated memory device. The device includes a set of a first memory cell array and a second memory cell array having word lines, a row decoding unit which simultaneously activates the first memory cell array and the second memory cell array, and pairs of input and output lines through which data transfer from and to the first memory cell array and the second memory cell array. The row decoding unit includes a decoder which decodes the row address, a first word line driver, and a second word line driver. The first word line driver, which connects to the power supply voltage, transmits the decoded row address to the first memory cell array so as to select the word lines corresponding to the row address among the word lines of the first memory cell array.

Abstract: A semiconductor memory device includes a memory cell array divided into a plurality of sub-arrays. The number of memory cells per bit line in at least one of the sub-arrays differs from the number of memory cells per bit line in other sub-arrays. When the sense amplifiers can accommodate a bit line loading of (2M+2M/N) memory cells per bit line, the size and bit line loading of one of more of the sub-arrays can be increased. This can provide sub-arrays of different sizes and can reduce the number of the sub-arrays and the number of the sense amplifier regions. Accordingly, the chip efficiency is improved. Maximum current for sensing during simultaneous accesses of multiple arrays can access two sub-arrays with different bit line loadings and avoid simultaneously accessing two sub-arrays having high bit-line loadings.

Abstract: There is provided a semiconductor memory device which includes a plurality of memory cell blocks arranged in rows and columns. Each memory cell block includes a plurality of memory cells for storing data. A plurality of data input/output circuits are divided into a first group and a second group. The first group and the second group are associated with and disposed between a respective subset of the memory cell blocks. The data input/output circuits have a plurality of data input/output pins. A plurality of address signal circuits are arranged between the first group and the second group for receiving externally applied address signals. The semiconductor memory device is packed using a Non-Outer-DQ-Inner-Control (NON-ODIC) type package having a structure such that the data input/output pins of the data input/output circuits of the first and second groups are collectively arranged adjacent to each other.

Abstract: An integrated circuit memory device includes a memory cell block including a memory cell array which has a plurality of odd and even numbered subword lines extending therethrough. A first decoder is disposed at a top side of the memory cell block, which receives a first row address and generate a plurality of first control signals in response thereto. A second decoder is disposed at a bottom side of the memory cell block, which receives the first row address and generate a plurality of second control signals in response thereto. A row decoder receives a second row address and generates a word line signal in response thereto.

Abstract: A row redundancy fuse box that replaces a defective row with a redundant row of an integrated circuit memory device is located between a row decoder, a row predecoder and a subarray block control circuit. By locating the row redundancy fuse box between the row decoder and the subarray block control circuit, the size of an integrated circuit memory device and the bus line loading in the device may be reduced. A row predecoder is coupled to the row redundancy fuse box and is located remote from the row decoder, the subarray block control circuit and the row redundancy fuse box. A column decoder is located adjacent the row predecoder and remote from the row decoder, the subarray block control circuit and the row redundancy fuse box. A pad layer receives and transmits external input and output signals respectively, and is located adjacent the subarray block control circuit, opposite the row redundancy fuse box.

Abstract: Integrated circuit memory devices include a rectangular integrated circuit memory device substrate that includes a pair of short sides, a pair of long sides and a pair of opposing faces. The substrate also includes an array of memory cells and peripheral circuits therein. A plurality of spaced apart rows of input/output pads on one of the faces extend parallel to the short sides. The face is free of (i.e. does not include) a row of input/output pads that extends parallel to the long sides. The input/output pads are preferably arranged on the integrated circuit memory device substrate, relative to the circuits in the integrated circuit memory device substrate. More specifically, the integrated circuit memory device includes a plurality of memory cell array blocks, first decoder blocks and second decoder blocks in the substrate. A respective first decoder block extends parallel to the short sides adjacent a respective memory cell array block and opposite a short side.

Abstract: A dynamic random access memory device includes sub-word line drivers to drive sub-word lines up to a boosted voltage level. Each sub-word line driver generates a sub-word drive signal to drive a corresponding sub-word line in response to main-word decode signal and a sub-word decode signal. Each of the sub-word line drivers includes an N-channel MOS pull-up transistor and an N-channel MOS precharge transistor whose threshold voltages are different from each other. The conduction path of the pull-up transistor is coupled between the sub-word decode signal and the corresponding sub-word line. The precharge transistor has a conduction path coupled between the main-word line and the control electrode of the pull-up transistor. The control electrode of the precharge transistor is coupled to the boosted voltage. The boosted voltage is larger than the power supply voltage by twice the threshold voltage of the pull-up transistor.