Abstract: A vehicle seat reinforcement device includes a leg portion mounted on a floor panel, a seat cushion frame slidably mounted on the leg portion, and a load reinforcing structure connected between the leg portion and the seat cushion frame, wherein when a seat belt anchorage load is transferred to the seat cushion frame, the seat cushion frame is locked to the leg portion by the load reinforcing structure.

Abstract: Memory array structures, and methods of their formation, might include a first memory cell having a first control gate and an adjacent first portion of a charge-blocking structure, a second memory cell having a second control gate and an adjacent second portion of the charge-blocking structure, and a first dielectric material between the first control gate and the second control gate, and adjacent to a third portion of the charge-blocking structure that is between the first and second portions of the charge-blocking structure. The third portion of the charge-blocking structure might include a second dielectric material and a third dielectric material different than the second dielectric material, and the first portion of the charge-blocking structure and the second portion of the charge-blocking structure might each include the third dielectric material and a fourth dielectric material different than the second dielectric material. Apparatus might include such memory array structures.

Abstract: A semiconductor package includes a substrate, a grounding layer, a chip, a package body, and a shielding layer. The substrate includes a lateral surface and a bottom surface. The grounding layer is buried in the substrate and extends horizontally in the substrate. The chip is arranged on the substrate. The package body envelops the chip and includes a lateral surface. The shielding layer covers the lateral surface of the package body and the lateral surface of the substrate, and is electrically connected to the grounding layer, where a bottom surface of the shielding layer is separated from a bottom surface of the substrate.

Abstract: The present disclosure relates to a semiconductor package and a method of fabricating the same. The semiconductor package includes a substrate, a grounding layer, a chip, a package body, and a shielding layer. The substrate includes a lateral surface and a bottom surface. The grounding layer is buried in the substrate and extends horizontally in the substrate. The chip is arranged on the substrate. The package body envelops the chip and includes a lateral surface. The shielding layer covers the lateral surface of the package body and the lateral surface of the substrate, and is electrically connected to the grounding layer, where a bottom surface of the shielding layer is separated from a bottom surface of the substrate.

Abstract: Disclosed is a method for fabricating a cliché that can prevent formation of a defective thin film pattern, and a method for forming a thin film pattern using the same. The method for fabricating a cliché includes providing a base substrate having first and second regions, forming a first depressed pattern having a first depth and a first width at a first region, and a second depressed pattern having a second width greater than the first width and a depth the same with the first depth at a second region, forming a protective film for exposing the second region and covering the first region, the protective film having adhesivity, forming the second depressed pattern to have a second depth deeper than the first depth of the first depressed pattern at the first region by using the protective film having the adhesivity, and removing the protective film.

Abstract: An earphone antenna of a portable terminal having enhanced reception sensitivity even when a wearing state of the earphone of the mobile terminal is changed is provided. The earphone antenna includes a plurality of voice signal lines, an insulating sheath configured to cover an outer surface of the plurality of the voice signal lines, a receptacle configured to connect to a first end of each of the plurality of the voice signal lines, and a ground and antenna line including a first antenna line configured to wind around an outer surface of the insulating sheath at a first interval in a spiral form, the first antenna line having a first thickness, wherein the ground and antenna line includes a second antenna line configured to wind around an outer surface of the receptacle at a second interval in the spiral form, the second antenna line having a second thickness that is greater than the first thickness and the second interval being different from the first interval.

Abstract: A semiconductor package that can fit semiconductor chips of various sizes without having to change the footprint of the carrier package. One aspect of the semiconductor package comprises a leadframe, a semiconductor chip attached to the leadframe, electrical connectors electrically connecting the semiconductor chip to the leadframe, and a sealing material. The leadframe has a plurality of leads, with each one of the plurality of leads having an upper side, a lower exposed side, and a laterally exposed side. The upper side of each one of the plurality of leads defines a generally co-planar surface. Further, after sealing material encapsulates the components of the semiconductor package in a spatial relationship, the lower exposed side and the lateral exposed side of the plurality of leads are exposed to the outside surface of the semiconductor package.

Abstract: An earphone antenna of a portable terminal having enhanced reception sensitivity even when a wearing state of the earphone of the mobile terminal is changed is provided. The earphone antenna includes a plurality of voice signal lines, an insulating sheath configured to cover an outer surface of the plurality of the voice signal lines, a receptacle configured to connect to a first end of each of the plurality of the voice signal lines, and a ground and antenna line including a first antenna line configured to wind around an outer surface of the insulating sheath at a first interval in a spiral form, the first antenna line having a first thickness, wherein the ground and antenna line includes a second antenna line configured to wind around an outer surface of the receptacle at a second interval in the spiral form, the second antenna line having a second thickness that is greater than the first thickness and the second interval being different from the first interval.

Abstract: Disclosed is a method for fabricating a cliché that can prevent formation of a defective thin film pattern, and a method for forming a thin film pattern using the same. The method for fabricating a cliché includes providing a base substrate having first and second regions, forming a first depressed pattern having a first depth and a first width at a first region, and a second depressed pattern having a second width greater than the first width and a depth the same with the first depth at a second region, forming a protective film for exposing the second region and covering the first region, the protective film having adhesivity, forming the second depressed pattern to have a second depth deeper than the first depth of the first depressed pattern at the first region by using the protective film having the adhesivity, and removing the protective film.

Abstract: A chip scale package includes a patterned circuit layer attached to the active surface of a semiconductor chip through an anisotropic conductive adhesive layer such that contact pads on a lower surface of the patterned circuit layer are electrically coupled to corresponding bonding pads on the semiconductor chip. The patterned circuit layer has a plurality of openings formed therein at locations corresponding to the contact pads such that each of the contact pads has a portion exposed from an upper surface of the patterned circuit layer through the corresponding opening. A plurality of metal bumps are respectively disposed in the openings and mounted to the exposed portions of the contact pads for making external electrical connection. The present invention further provides a method for manufacturing the chip scale package at the wafer-level.

Abstract: A semiconductor device package includes a semiconductor device mounted and electrically coupled to a substrate, a package body encapsulating the semiconductor device against a portion of an upper surface of the substrate; and an electromagnetic interference shielding layer formed over the package body and substantially enclosing the semiconductor device. The present invention further provides methods for manufacturing the semiconductor device package.

Abstract: A semiconductor device package includes a semiconductor device mounted and electrically coupled to a substrate, a package body encapsulating the semiconductor device against a portion of an upper surface of the substrate; and an electromagnetic interference shielding layer formed over the package body and substantially enclosing the semiconductor device. The electromagnetic interference shielding layer is a plated metal layer in contact with the package body, and the plated metal layer is connected to a ground trace extending on the upper surface of the substrate.

Abstract: A semiconductor device package includes a semiconductor device mounted and electrically coupled to a substrate, a package body encapsulating the semiconductor device against a portion of an upper surface of the substrate; and an electromagnetic interference shielding layer formed over the package body and substantially enclosing the semiconductor device. The present invention further provides methods for manufacturing the semiconductor device package.

Abstract: A semiconductor package comprises a silicon substrate having an insulative surface; a patterned metal layer, formed on the insulative surface of the silicon substrate; an insulation layer formed on the patterned metal layer, and the patterned metal layer being partially exposed for functioning as at least a set of the device attaching pads and ball attaching pads; at least a device electrically connected to the set of the device attaching pads; a sealing compound for covering portions of the insulative surface of the silicon substrate and encapsulating the devices; and a plurality of solder balls attached to the set of ball attaching pads.

Abstract: A semiconductor device package includes a semiconductor device mounted and electrically coupled to a substrate, a package body encapsulating the semiconductor device against a portion of an upper of the substrate; and an electromagnetic interference shielding layer formed over the package body and substantially enclosing the semiconductor device. The present invention further provides methods for manufacturing the semiconductor device package.

Abstract: A semiconductor device package includes a semiconductor device mounted and electrically coupled to a substrate, a package body encapsulating the semiconductor device against a portion of an upper surface of the substrate; and an electromagnetic interference shielding layer formed over the package body and substantially enclosing the semiconductor device. The electromagnetic interference shielding layer is a plated metal layer in contact with the package body, and the plated metal layer is connected to a ground trace extending on the upper surface of the substrate.

Abstract: A die pick and place tool is used to pick up a semiconductor die and place it on a substrate. The die pick and place tool comprises a moving shaft, an adjustable bearing or an elastic element, and a pick-up head. The adjustable bearing or the elastic element is connected to the moving shaft. The pick-up head is connected to the adjustable bearing, and used to catch the semiconductor die. When the semiconductor die contacts the substrate, a counter force acts to the adjustable bearing to adjust the tilt level of the pick-up head.

Abstract: A multiple chip package module comprises a first substrate, a first chip, an inverted first semiconductor unit, a first encapsulant, and a second semiconductor unit. The first chip is disposed on the first substrate. The inverted first semiconductor unit is stacked over the first chip. The first encapsulant covers the first chip and the first semiconductor unit, and the first encapsulant has an opening to expose a part of the first semiconductor unit. The second semiconductor unit comprises a plurality of first bumps on a bottom side of the second semiconductor unit, the second semiconductor unit mounted on the first semiconductor unit in the opening, and is electrically connected to the first semiconductor unit through the first bumps.

Abstract: A semiconductor package comprises a silicon substrate having an insulative surface; a patterned metal layer, formed on the insulative surface of the silicon substrate; an insulation layer formed on the patterned metal layer, and the patterned metal layer being partially exposed for functioning as at least a set of the device attaching pads and ball attaching pads; at least a device electrically connected to the set of the device attaching pads; a sealing compound for covering portions of the insulative surface of the silicon substrate and encapsulating the devices; and a plurality of solder balls attached to the set of ball attaching pads.

Abstract: A semiconductor package includes a semiconductor device and a passive component mounted and electrically coupled to a substrate. The passive component is disposed within a cavity portion formed on an upper surface of the substrate and the semiconductor device is disposed across the cavity portion of the substrate above the passive component.