Abstract: A quad flat non-lead (QFN) package at least comprises a die, a lead frame and a molding compound. The lead frame comprises a plurality of L-shaped leads for electrically connecting the die. Two pre-plated conductive layers, formed on a bottom portion and a top portion of each L-shaped lead, are exposed to a bottom surface and a top surface of the package, respectively. The molding compound is formed for encapsulating the die and the L-shaped leads.

Abstract: An optic semiconductor package includes a main board of a substantially planar plate shape. The main board includes an aperture therethrough and a plurality of board metal patterns formed at the periphery of the aperture. A package portion is coupled to the main board. The package portion includes a base, a laser diode and a photo detector electrically coupled to the board metal patterns of the main board and bonded to the base. An optical fiber is inserted into the aperture of the main board and disposed adjacent the package portion. The position and tilt of the optical fiber may be adjusted to achieve optimum optical coupling between the optical fiber and the laser diode and the optical fiber and the photo detector. The optical fiber is stably attached to the main board by an adhesive.

Abstract: The fabrication and device of package structure with a plurality of conductive contacts are provided herein. At least one chip is attached among the conductive pads on the surface of a wafer. A number of conductive wires are attached on the conductive pads and encapsulated by a layer. The layer is removed from the top thereof until to expose the conductive contacts derived from the conductive wires.

Abstract: A semiconductor package includes a semiconductor device and a passive component mounted and electrically coupled to a substrate. The passive component is disposed within a cavity portion formed on an upper surface of the substrate and the semiconductor device is disposed across the cavity portion of the substrate above the passive component.

Abstract: Leadframe-type semiconductor packages that allow the semiconductor packages to be stacked on top of each other. One aspect of the semiconductor package includes a leadframe, a plurality of electrical connectors, a semiconductor chip, and a sealing material for encapsulating the above components. The leadframe has a plurality of leads, with each one of the plurality of leads running from the top of the semiconductor package to the bottom of the semiconductor package. Each one of the plurality of leads has a top portion protruding from the top surface of the semiconductor package and a bottom portion protruding from the top surface of the semiconductor package and a bottom portion protruding from the bottom surface of the semiconductor package. The leads allow for electrical connection of a second semiconductor package placed on top of the first semiconductor package. Further, the protruding parts of the leads form a space between the stacked semiconductor packages for improved heat dissipation.

Abstract: A singulation method used in a process for making a plurality of image sensor packages is disclosed. Firstly, a semi-finished product including a plurality of package structures formed on a substrate is placed on a support having a plurality of cavities for receiving the package structures. Then, the semi-finished product is sawed into separate image sensor packages. During the sawing step, the air pressure in the cavities is decreased to create suction within the cavities such that the support abuts against at least a portion of the housing of each package structure with a gap between the transparent component and the support whereby the package structures are positioned precisely and clamped in place with the support during the sawing step.

Abstract: A semiconductor package including passive elements and a method of manufacturing provide reduced package size, improved performance and higher process yield by mounting the passive elements beneath the semiconductor die on the substrate. The semiconductor die may be mounted above the passive elements by mechanically bonding the semiconductor die to the passive elements, mounting the passive elements within a recess in the substrate or mounting the semiconductor using an adhesive retaining wall on the substrate that protrudes above and extends around the passive elements. The recess may include an aperture through the substrate to vent the package to the outside environment or may comprise an aperture through the substrate and larger than the semiconductor die, permitting the encapsulation to entirely fill the aperture, covering the die and the passive elements to secure them mechanically within the package.

Abstract: A multi-chip image sensor package module includes a substrate having an opening, an IC chip, an image sensor chip and a glass cover. The IC chip includes a plurality of bumps on its mounting surface to mount on the lower surface of the substrate. The glass cover is disposed above the upper surface of the substrate. The image sensor chip is disposed between the mounting surface of the IC chip and the upper surface of the substrate by chip-to-chip attachment or flip-chip connection in a manner that the sensing region of the image sensor chip is aligned with the glass cover or a lens through the opening. Thus the multi-chip image sensor package module can have a thinner profile with lower assemble cost.

Abstract: An image sensor package module with a leadless leadframe between chips includes a chip carrier, an image sensor chip, an integrated circuit chip, and a flexible printed circuit board. The chip carrier comprises a leadless leadframe and a pre-molded body. The leadless leadframe has a plurality of leads. The pre-molded body is completely filled among the leads and has a dam on the upper surfaces of the leads. The upper surfaces and lower surfaces of the leads are exposed on the pre-molded body. The image sensor chip is attached to the chip carrier inside the dam and electrically connected to the upper surfaces of the leads. The integrated circuit chip is mounted on the lower surfaces of the leads via bumps. The flexible printed circuit board is electrically connected to the leads for signal transmission.

Abstract: A semiconductor package comprising a low temperature co-fired ceramic substrate defining opposed top and bottom surfaces. The substrate comprises at least two stacked ceramic layers and electrically conductive patterns which extend between the layers and along the top surface of the substrate. Mounted to the top surface of the substrate and electrically connected to the conductive patterns is at least one semiconductor die. A plurality of leads extend at least partially about the substrate in spaced relation thereto. Each of the leads defines opposed top and bottom surfaces, the semiconductor die being electrically connected to at least one of the leads. A package body at least partially encapsulates the substrate, the semiconductor die and the leads such that at least a portion of the bottom surface of each of the leads is exposed in the package body.

Abstract: A stackable semiconductor package having a lead frame, a plurality of electrical paths, and a sealing material. The leadframe has a plurality of leads, each one of the plurality of leads having a top portion exposed to a top surface of the semiconductor package and a bottom portion resting flush with a bottom surface of the semiconductor package. In this manner, the leads extending from the top surface to the bottom surface of the semiconductor package provide an electrical path for connecting and electrically powering a second semiconductor package stacked on top of a first bottom semiconductor package.

Abstract: A semiconductor package that can fit semiconductor chips of various sizes without having to change the footprint of the carrier package. One aspect of the semiconductor package comprises a leadframe, a semiconductor chip attached to the leadframe, electrical connectors electrically connecting the semiconductor to the leadframe, and a sealing material. The leadframe has a plurality of leads, with each one of the plurality of leads having an upper side, a lower exposed side, and a laterally exposed side. The upper side of each one of the plurality of leads define a generally co-planar surface. Further, after sealing material encapsulates the components of the semiconductor package in a spacial relationship, the lower exposed side and the lateral exposed side of the plurality of leads are exposed to the outside surface of the semiconductor package.

Abstract: An optic semiconductor package includes a main board of a substantially planar plate shape. The main board includes an aperture therethrough and a plurality of board metal patterns formed at the periphery of the aperture. A package portion is coupled to the main board. The package portion includes a base, a laser diode and a photo detector electrically coupled to the board metal patterns of the main board and bonded to the base. An optical fiber is inserted into the aperture of the main board and disposed adjacent the package portion. The position and tilt of the optical fiber may be adjusted to achieve optimum optical coupling between the optical fiber and the laser diode and the optical fiber and the photo detector. The optical fiber is stably attached to the main board by an adhesive.

Abstract: An optic semiconductor package includes a plate shaped substrate having an insulation layer through which two spaced apart layer apertures are formed. The substrate further includes a plurality of electrically conductive patterns formed on the wall surfaces of the layer apertures and a lower surface of the insulation layer. One of a laser diode and a photo detector are disposed in a different one of the two layer apertures and are each electrically connected to the electrically conductive patterns through conductive bumps formed on the laser diode and the photo detector. An insulation plate, having a plurality of plate apertures formed through portions of the insulation plate adjacent to the electrically conductive patterns, is coupled to the lower surface of the substrate. One of a plurality of conductive pins electrically connected with the electrically conductive patterns is fitted in each of the plate apertures of the insulation plate and extends downward from the insulation plate.

Abstract: A semiconductor package that can fit semiconductor chips of various sizes without having to change the footprint of the carrier package. One aspect of the semiconductor package comprises a leadframe, a semiconductor chip attached to the leadframe, electrical connectors electrically connecting the semiconductor to the leadframe, and a sealing material. The leadframe has a plurality of leads, with each one of the plurality of leads having an upper side, a lower exposed side, and a laterally exposed side. The upper side of each one of the plurality of leads define a generally co-planar surface. Further, after sealing material encapsulates the components of the semiconductor package in a spacial relationship, the lower exposed side and the lateral exposed side of the plurality of leads are exposed to the outside surface of the semiconductor package.

Abstract: Micro lead frame (MLF)-type semiconductor packages that allow the semiconductor packages to be stacked on top of each other. One aspect of the semiconductor package includes a leadframe, a plurality of electrical connectors, a semiconductor chip, and a sealing material for encapsulating the above components. The leadframe has a plurality of leads, with each one of the plurality of leads running from the top of the semiconductor package to the bottom of the semiconductor package. Each one of the plurality of leads has a top portion protruding from the top surface of the semiconductor package and a bottom portion protruding from the bottom surface of the semiconductor package. The leads allow for electrical connection of a second semiconductor package placed on top of the first semiconductor package. Further, the protruding parts of the leads form a space between the stacked semiconductor packages for improved heat dissipation.

Abstract: Micro lead frame (MLF)-type semiconductor packages that allow the semiconductor packages to be stacked on top of each other. One aspect of the semiconductor package includes a leadframe, a plurality of electrical connectors, a semiconductor chip, and a sealing material for encapsulating the above components. The leadframe has a plurality of leads, with each one of the plurality of leads running from the top of the semiconductor package to the bottom of the semiconductor package. Each one of the plurality of leads has a top portion protruding from the top surface of the semiconductor package and a bottom portion protruding from the bottom surface of the semiconductor package. The leads allow for electrical connection of a second semiconductor package placed on top of the first semiconductor package. Further, the protruding parts of the leads form a space between the stacked semiconductor packages for improved heat dissipation.

Abstract: A semiconductor package has a substrate of an approximate planar plate comprising of an insulative layer having a plurality of land holes formed in the vicinity of an inner circumference thereof and a plurality of electrically conductive patterns formed at a surface of the insulative layer, the electrically conductive patterns comprising a plurality of bond fingers formed in the vicinity of a central portion of the insulative layer and a plurality of lands for covering the land holes connected to the bond fingers. A semiconductor die is located at a central portion of the substrate. The semiconductor die has a plurality of bond pads formed at one surface thereof. A plurality of conductive bumps is used for coupling the bond pads of the semiconductor die to the bond fingers among the electrically conductive patterns of the substrate.

Abstract: A circuit board for semiconductor package is designed to provide a complete grounding with corresponding equipment in the manufacture of the semiconductor package based on a circuit board, thereby preventing a breakdown of the circuit board or semiconductor chip caused by electrostatic charges.

Abstract: A semiconductor package including passive elements and a method of manufacturing provide reduced package size, improved performance and higher process yield by mounting the passive elements beneath the semiconductor die on the substrate. The semiconductor die may be mounted above the passive elements by mechanically bonding the semiconductor die to the passive elements, mounting the passive elements within a recess in the substrate or mounting the semiconductor using an adhesive retaining wall on the substrate that protrudes above and extends around the passive elements. The recess may include an aperture through the substrate to vent the package to the outside environment or may comprise an aperture through the substrate and larger than the semiconductor die, permitting the encapsulation to entirely fill the aperture, covering the die and the passive elements to secure them mechanically within the package.