Abstract: An organic light-emitting display device and a method of its manufacture are provided, whereby manufacturing processes are simplified and display quality may be enhanced. The display device includes: an active layer of a thin film transistor (TFT), on a substrate and including a semiconducting material; a lower electrode of a capacitor, on the substrate, doped with ion impurities, and including a semiconducting material; a first insulating layer on the substrate to cover the active layer and the lower electrode; a gate electrode of the TFT, on the first insulating layer; a pixel electrode on the first insulating layer; an upper electrode of the capacitor, on the first insulating layer; source and drain electrodes of the TFT, electrically connected to the active layer; an organic layer on the pixel electrode and including an organic emission layer; and a counter electrode facing the pixel electrode, the organic layer between the counter electrode and the pixel electrode.

Abstract: An OLED display including a substrate main body; a first gate electrode and a second semiconductor layer; a gate insulating layer on the first gate electrode and the second semiconductor layer; a first semiconductor layer and a second gate electrode overlying the first gate electrode and the second semiconductor layer, respectively; etching stopper layers contacting portions of the first semiconductor layer; an interlayer insulating layer on the first semiconductor layer and the second gate electrode and including contact holes exposing the plurality of etching stopper layers, respectively; a first source electrode and a first drain electrode on the interlayer insulating layer and the contact holes being indirectly connected to the first semiconductor layer via the etching stopper layers or directly connected to the first semiconductor layer; and a second source electrode and a second drain electrode on the interlayer insulating layer being connected to the second semiconductor layer.

Abstract: A gate driving apparatus includes a first stage which outputs a first gate output signal, and a second stage which outputs a second gate output signal. The first stage includes: a transistor which includes a gate electrode, a source electrode and a drain electrode; and a dummy transistor which includes a dummy gate electrode, a dummy source electrode and a dummy drain electrode. The gate electrode receives the second gate output signal, and the dummy source electrode is connected to the source electrode or the drain electrode of the transistor and prevents static electricity from flowing to the first stage.

Abstract: A flat panel display device that can achieve uniformity between pixel circuits and improved image quality includes: a first pixel including a first light emitting device and not including a pixel circuit; and a second pixel spaced apart from the first pixel and including a first circuit that is electrically connected to the first light emitting device. Active layers of thin film transistors in the pixel circuits are formed of polycrystalline silicon crystallized from an amorphous silicon and patterned from an area of the polycrystalline silicon in which lasers of an excimer laser annealing process did not overlap.

Abstract: A method for forming a plurality of metal lines in a semiconductor device including forming first insulating layer patterns on a semiconductor substrate, the first insulating patterns being spaced from each other; depositing a metal layer on and between the first insulating layer patterns; planarizing the metal layer; patterning the planarized metal layer to form the plurality of metal lines between the first insulating layer patterns; and forming a second insulating layer on and between the metal lines.

Abstract: A method for forming a plurality of metal lines in a semiconductor device including forming first insulating layer patterns on a semiconductor substrate, the first insulating patterns being spaced from each other; depositing a metal layer on and between the first insulating layer patterns; planarizing the metal layer; patterning the planarized metal layer to form the plurality of metal lines between the first insulating layer patterns; and forming a second insulating layer on and between the metal lines.

Abstract: A method fabricating multiple wiring metals in a semiconductor device. The method includes forming a lower wiring metal on a semiconductor substrate, forming an interlayer dielectric on the lower wiring metal, and selectively removing the interlayer dielectric to form a contact dielectric film, a body dielectric film and an opening between the contact and body dielectric films. The method also includes filling the opening with low-k material, forming a capping dielectric on the contact and body dielectric films and the low-k material, forming a contact hole passing through the capping dielectric and the contact dielectric film to be connected to the lower wiring metal, and forming an upper wiring metal electrically interconnected to the lower wiring metal through the contact hole.

Abstract: A semiconductor device with a metal line and a method of forming the same. The method includes forming an insulation layer on a semiconductor substrate including a predetermined lower structure, forming a vertical hole and a horizontal hole by etching the insulation layer, forming a supporting part by filling the vertical holes and horizontal holes with a nitride layer, and forming a damascene metal line layer by forming a metal line on the insulation layer. The method also includes performing the forming process for the damascene metal line layer a plurality of times, removing the insulation layer, and forming a protective layer on the highest layer of the damascene metal line layer.

Abstract: An apparatus for atomic layer deposition (ALD) and methods for manufacturing a semiconductor device using the same. In one example embodiment, an ALD apparatus includes a heater, a plasma device, a distance control unit, and a controller. The heater is configured to have a semiconductor substrate mounted thereon. The plasma device is positioned opposite an upper side of the heater. The distance control unit is configured to control a distance between the plasma device and the semiconductor substrate. The controller is configured to determine whether the semiconductor substrate has been plasma-damaged by the plasma device.

Abstract: An HDP-CVD apparatus includes a valve assembly, a pump, and a control unit for adjusting the supply of He gas to be within a preset range through control of the valve assembly and the pump so that an actual wafer temperature, which was previously determined, is maintained at a preset temperature during a deposition process.

Abstract: A method fabricating multiple wiring metals in a semiconductor device. The method includes forming a lower wiring metal on a semiconductor substrate, forming an interlayer dielectric on the lower wiring metal, and selectively removing the interlayer dielectric to form a contact dielectric film, a body dielectric film and an opening between the contact and body dielectric films. The method also includes filling the opening with low-k material, forming a capping dielectric on the contact and body dielectric films and the low-k material, forming a contact hole passing through the capping dielectric and the contact dielectric film to be connected to the lower wiring metal, and forming an upper wiring metal electrically interconnected to the lower wiring metal through the contact hole.

Abstract: A semiconductor device with a metal line and a method of forming the same. The method includes forming an insulation layer on a semiconductor substrate including a predetermined lower structure, forming a vertical hole and a horizontal hole by etching the insulation layer, forming a supporting part by filling the vertical holes and horizontal holes with a nitride layer, and forming a damascene metal line layer by forming a metal line on the insulation layer. The method also includes performing the forming process for the damascene metal line layer a plurality of times, removing the insulation layer, and forming a protective layer on the highest layer of the damascene metal line layer.