Abstract: A method for forming a chess-board patterned bond pad structure with stress buffered characteristics and the bond pad structure formed are disclosed. In one method, a multiplicity of field oxide regions are first formed in the surface of a silicon substrate. A conductive layer such as polycide is then deposited and formed on the substrate to form a stepped surface with a metal layer subsequently deposited on top of the conductive layer to form a bond pad. The stepped structure reproduced on the metal layer serves to distribute bonding stresses during a wire bonding process such that bond pad lift-off defects are substantially eliminated. In another method, the conductive layer is first formed into conductive gates with insulating sidewalls formed subsequently. Similarly stepped surface on a metal layer can be obtained to realize the stress buffered characteristics of the novel method.

Abstract: A method to remove the silicon nitride capacitor dielectric layer from over the poly-1 layer on portions of the wafer including non-capacitor areas such as the pad contact area, process control monitor (PCM) testsite areas and scribe line areas. By removing the silicon nitride, H2 can penetrate to the polysilicon and thereby increase the uniformity of the VT. In a first embodiment of the invention, the silicon nitride capacitor dielectric layer is etched away from over the poly-1 layer in the pad area. The removal of the SiN layer allows H2 to penetrate into the poly-1 layer and improve the threshold voltage (VT). Uniformity of long channel VT-N was improved when we modify the pad struture of PCM to increase the clear out ratio of capacitor Si3N4 to 1.0584%. In a second embodiment of the invention, the silicon nitride capacitor dielectric is etched away from over the poly-1 layer in the process control monitor (PCM) testsite area between the chips.

Abstract: Sewage water containing phosphate is passed through an anaerobic treatment chamber containing reductive-iron-dissolution (RID) material, such as ferric oxyhydroxide solids. The RID material releases ferrous ions into solution, which combine with the phosphate to produce ferrous-phosphate minerals, such as vivianite, which precipitate in the anaerobic chamber. Also, iron and phosphate remaining in the water can precipitate as ferric-phosphate minerals such as strengite, when the water is later aerated.

Abstract: An improved bond pad structure for semiconductor devices provides improved electrical isolation between adjacent bond pads by incorporating a pair of pn junctions between the pad and substrate. The pn junctions are defined by a first well of either P of N type material, formed within a substrate, and a second well or region of a P or N type material formed wholly within the first well. A bond wire is secured to an upper surface of the second region such that the wire, first and second regions and substrate are connected in electrical series relationship and provide an equivalent circuit of two series connected diodes reversed in polarity so as to block both negative and positive components of an applied voltage, thus providing electrical isolation for the bond pad structure.

Abstract: A method for forming a p-type halo implant as ROM cell isolation in a flat-cell mask ROM process is described. A P-well is formed within a semiconductor substrate and an oxide layer is formed overlying a surface of the substrate. A photomask is formed overlying the oxide layer wherein openings are left within the photomask exposing portions of the oxide layer. First, ions are implanted through the exposed portions of the oxide layer into the underlying semiconductor substrate whereby buried bit lines are formed. Thereafter, second ions are implanted through the exposed portions of the oxide layer whereby halo regions are formed encompassing the buried bit lines. The halo regions provide ROM isolation and punch-through protection for the buried bit lines. Thereafter, the photomask is removed and fabrication of flat-cell mask ROM device is completed.

Abstract: A method for forming a metal oxide semiconductor field effect transistor (MOSFET). There is first provided a semiconductor substrate. There is then formed upon the semiconductor substrate a gate dielectric layer. There is then formed upon the gate dielectric layer a gate electrode. There is then implanted into the semiconductor substrate while employing the gate electrode as a mask a pair of unactivated source/drain regions at a pair of opposite edges of the gate electrode, where the gate dielectric layer, the gate electrode and the pair of unactivated source/drain regions form an unactivated metal oxide semiconductor field effect transistor (MOSFET).

Abstract: A method is disclosed for improving the ESD protection of gate oxide in ultra large scale integrated circuits of 0.35 .mu.m technology or less, approaching 0.25 .mu.m. This is accomplished by providing a silicon substrate and forming thereon product FET device circuits and ESD protection device circuits. In forming the ESD source/drain regions, the implantation species is changed from phosphorous to boron, thereby reducing junction breakdown voltage. Ion implantation is performed judiciously in areas with high leakage and capacitance. Hence improvement is accomplished though reduced breakdown voltage, as well as through reduced leakage and capacitance of the junction. Furthermore, ion implantation is performed using a photoresist mask prior to the formation of silicidation over the contact area. This avoids the problem of silicide degradation and the concomitant increase in contact resistance through the transportation of metal ions into depletion region of junction during high energy ESD implantation.

Abstract: A method for forming a chess-board patterned bond pad structure with stress buffered characteristics and the bond pad structure formed are disclosed. In one method, a multiplicity of field oxide regions are first formed in the surface of a silicon substrate. A conductive layer such as polycide is then deposited and formed on the substrate to form a stepped surface with a metal layer subsequently deposited on top of the conductive layer to form a bond pad. The stepped structure reproduced on the metal layer serves to distribute bonding stresses during a wire bonding process such that bond pad lift-off defects are substantially eliminated. In another method, the conductive layer is first formed into conductive gates with insulating sidewalls formed subsequently. Similarly stepped surface on a metal layer can be obtained to realize the stress buffered characteristics of the novel method.

Abstract: The present invention is a method of protecting an alignment mark in semiconductor manufacturing process with CMP. This invention utilizes a via mask or masking blade to remove the intermetal dielectric layer on a wide clear -out window using two etching steps. One etching step is performed before intermetal dielectric layer polish. The other etching step is performed after intermetal dielectric layer polish. Thus, there is no intermetal dielectric layer remained on the alignment mark and the alignment mark keeps the original shape.

Abstract: This invention relates to a method for removing residual spin-on-glass (SOG) during a planarization processing step wherein the SOG is used as a sacrificial planarization medium and subjected to a full etchback to an underlying interlevel dielectric (ILD) layer. The SOG is applied over the ILD layer, and etched back into the ILD layer by reactive-ion-etching under conditions of comparable etch rates for both SOG and ILD. At endpoint there some residual pockets of SOG can be present as well as a region of SOG along the edges of the wafer where it is clamped in the etchback tool. The residual SOG must be removed completely to avoid SOG cracking after thermal processing and SOG outgassing during subsequent metal deposition. For this purpose an aqueous etch consisting of hydrofluoric acid buffered with ammonium fluoride is used.

Abstract: A method for selectively depositing a silicon oxide insulator spacer layer between multi-layer patterned metal stacks within an integrated circuit. Formed upon a semiconductor substrate is a silicon oxide insulator substrate layer which is formed through a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. Upon the silicon oxide insulator substrate layer are formed multi-layer patterned metal stacks. The multi-layer patterned metal stacks have a top barrier metal layer formed from titanium nitride and a lower-lying conductor metal layer formed from an aluminum containing alloy. Formed selectively upon the portions of the silicon oxide insulator substrate layer exposed through the multi-layer patterned metal stacks and upon the edges of the aluminum containing alloy exposed through the multi-layer patterned metal stacks is a silicon oxide insulator spacer layer.

Abstract: A method of forming a field oxide isolation region with reduced bird's beak length and planar topography is described. A first layer of pad oxide is formed on the surface of a silicon substrate. A layer of silicon nitride is formed on the surface of the first pad oxide layer. The silicon nitride layer and part of the first pad oxide layer are patterned to form an opening for the field oxide isolation region. The first pad oxide layer is removed in the area defined by the opening and simultaneously a cavity is formed in the first pad oxide layer under the silicon nitride. A second pad oxide layer is formed by oxidizing the exposed portions of the silicon substrate and the first pad oxide layer. A layer of polysilicon is deposited over the surfaces of the second pad oxide layer and the silicon nitride layer, and inside the cavity. The polysilicon layer is etched to form a polysilicon spacer adjacent to the silicon nitride layer and a polysilicon plug in the cavity.