Abstract: A method of fabrication an array substrate which includes foaming an oxide semiconductor layer on a substrate; forming a gate insulating layer corresponding to a central portion of the oxide semiconductor layer; forming a first reactive metallic pattern and second reactive metallic patterns on the gate insulating layer and portions of the oxide semiconductor layer exposed outside the gate insulating layer, respectively; forming a gate electrode on the first reactive metallic pattern; forming source and drain areas having conductive properties in the oxide semiconductor layer by performing heat treatment such that materials of the second reactive metallic patterns are diffused into the oxide semiconductor layer contacting the second reactive metallic patterns; forming an inter insulating layer on the gate electrode and having first contact holes that expose the second reactive metallic patterns; and forming source and drain electrodes on the inter insulating layer and contacting the second reactive metallic pa

Abstract: A power module includes a first substrate, at least two power elements, at least one first conductive structure and at least one leadframe. The first substrate includes a dielectric frame, two first fan-out circuit structure layers and two dielectric plates. The two first fan-out circuit structure layers are respectively disposed on two opposite surfaces of the dielectric frame, the two dielectric plates are respectively disposed on the two first fan-out circuit structure layers, each of the dielectric plates has at least one opening, and the opening and the corresponding first fan-out circuit structure layer form a concavity. The two power elements are respectively embedded in the two concavities. The two power elements are electrically connected to each other through the first conductive structure. The leadframe disposed at the first substrate is electrically connected to the two power elements, and is partially extended outside the first substrate.

Abstract: A depth information-based modeling method, a graphic processing apparatus and a storage medium are provided. The depth information-based modeling method includes receiving a plurality of depth image data, each of which has depth information, and a plurality of color images, each of which color information. In the method, a plurality of 3D grids is obtained according to the color information, depth information and a plurality of uniform sampling grids. Each of the uniform sampling grids is further divided into a plurality of sub-grids. At least one point on each of the 3D grids is determined by the depth information, and the triangle meshes are generated according to the points.

Abstract: A filter unit may include an electrode structure, a fluid-purifying flow path, and a pH adjusting chamber. The electrode structure may include a cathode, a cation exchange membrane, an anion exchange membrane, and an anode in that order. The fluid-purifying flow path may be at least one of a path in the cathode, between the cathode and the cation exchange membrane, between the anion exchange membrane and the anode, and in the anode. The fluid-purifying flow path may include an adsorption function. The pH adjusting chamber may be between the cation exchange membrane and the anion exchange membrane. The pH adjusting chamber may be configured to control the pH of the fluid in the fluid-purifying flow path.

Abstract: Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is a method of forming an interconnect structure, the method including forming a first post-passivation interconnect (PPI) over a first substrate, forming a second PPI over the first substrate, and forming a first conductive connector on the first PPI. The method further includes forming a second conductive connector on the second PPI, and forming a molding compound on top surfaces of the first and second PPIs and surrounding portions of the first and second connectors, a first section of molding compound being laterally between the first and second connectors, the first section of molding compound having a curved top surface.

Abstract: An integrated circuit includes a bottom substrate, a metal layer disposed over the bottom substrate and a hollow metal pillar disposed on the metal layer. The metal layer and the hollow metal pillar are electrically connected.

Abstract: A method of manufacturing a particle-based image display having a plurality of imaging cells is disclosed. The method includes filling the plurality of imaging cells with a plurality of first particles, identifying a defect associated with one or more of the imaging cells, and repairing the defect within a unit corresponding to part of the plurality of imaging cells.

Abstract: A packaged semiconductor device includes a semiconductor substrate, a metal pad, a metal base, a polymer insulating layer, a copper-containing structure and a conductive bump. The metal pad and the metal base are disposed on the semiconductor substrate. The polymer insulating layer overlies the metal base and the semiconductor substrate. The copper-containing structure is disposed over the polymer insulating layer, and includes a support structure and a post-passivation interconnect (PPI) line. The support structure is aligned with the metal base. The PPI line is located partially within the support structure, and extends out through an opening of the support structure, in which a top of the support structure is elevated higher than a top of the PPI line. The conductive bump is held by the support structure.

Abstract: An apparatus comprises an output port for a circuit load, a first input port for an energy harvest source, an input/output port a second energy source, a first circuit path from the energy harvest source to the second energy source at the input/output port and to the variable load at the output port, a second circuit path from the second energy source to the output port, a cold start circuit that produces a first voltage level at the output port by charging a capacitor at the output port using energy of the energy harvest source, and a main converter circuit that produces a second regulated voltage level at the input/output port using energy of the energy harvest source when the voltage at the output port capacitor is above a specified voltage value and uses the energy of the capacitor at the output port during startup of the main converter circuit.

Abstract: An oxide thin film transistor (TFT) includes an oxide semiconductor layer including a first semiconductor layer and a second semiconductor layer on the first semiconductor layer; a gate insulating layer on the oxide semiconductor layer; a gate electrode on the gate insulating layer; an interlayer insulating layer on the gate electrode; and a source electrode and a drain electrode on the interlayer insulating layer and contacting the oxide semiconductor layer, wherein a first reflectance of the first semiconductor layer is greater than a second semiconductor layer.

Abstract: A method of fabrication an array substrate includes forming an oxide semiconductor layer on a substrate; sequentially forming a gate insulating layer and a gate electrode corresponding to a central portion of the oxide semiconductor layer; forming source and drain areas having conductive properties in the oxide semiconductor layer by performing hydrogen plasma treatment; forming barrier layers on the source and drain areas, the barrier layer having a first thickness; forming an inter insulating layer on the gate electrode and having first contact holes that expose the barrier layers; and forming source and drain electrodes on the inter insulating layer and contacting the barrier layers through the first contact holes, respectively.

Abstract: A graphics processing method for three-dimensional images, applied to a first buffer for storing right-view contents and a second buffer for storing left-view contents, includes the following steps: when a current Vsync status indicates that a display engine is not operating within a right Vsync period of a right-view frame, the drawing engine drawing the right-view contents stored in first buffer; when current Vsync status indicates that the display engine is not operating within a left Vsync period of a left-view frame, the drawing engine drawing the left-view contents stored in second buffer; during the right Vsync period of the right-view frame, the display engine displaying right-view contents stored in first buffer; and during the left Vsync period of the left-view frame, the display engine displaying left-view contents stored in second buffer.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed, which can form a gate electrode material only in a recess of a buried gate cell structure, improve a Gate Induced Drain Leakage (GIDL) of a gate electrode material and a junction (i.e., drain region), prevent the gate electrode material from overlapping with the junction (i.e., drain region), and adjust the depth of junction, thereby improving channel resistance. The method for manufacturing a semiconductor device includes forming a device isolation region defining an active region over a semiconductor substrate, burying a gate electrode material in the semiconductor substrate, forming a gate electrode pattern by etching the gate electrode material, wherein the gate electrode pattern is formed at sidewalls of the active region including a source region, and forming a capping layer in the exposed active region.

Abstract: A method for electrodepositing copper nanoparticles includes the steps of a) providing a reaction system having an electrolyte solution, a conductive nitride film used as a working electrode and immersed in the electrolyte solution, a copper metal or a copper alloy used as an auxiliary electrode and immersed in the electrolyte solution, and a reference electrode immersed in the electrolyte solution; and b) applying a pulse voltage to the reaction system to form copper nanoparticles on a surface of the conductive nitride film.

Abstract: An array substrate including: a gate barrier layer on a substrate; a gate line on the gate barrier layer, the gate line having a gate open portion exposing the gate barrier layer in a gate electrode region; a gate insulating layer on the gate line; an active layer on the gate insulating layer over the gate barrier layer in the gate electrode region; and source and drain electrodes spaced apart from each other on the active layer.

Abstract: A semiconductor device includes one or more metal-insulator-metal (MiM) capacitors. The semiconductor device includes a bottom electrode, a dielectric layer located above, and in physical contact with, the bottom electrode, a top electrode located above, and in physical contact with, the dielectric layer, a first top contact contacting the top electrode, a first bottom contact contacting the bottom electrode from a top electrode direction, a first metal bump connecting to the top contact, and a second metal bump connecting to the bottom contact. The top electrode has a smaller area than the bottom electrode. The bottom electrode, the dielectric layer, and the top electrode is a MiM capacitor. Top electrodes of a number of MiM capacitors and bottom electrodes of a number of MiM capacitors are daisy chained to allow testing of the conductivity of the electrodes.

Abstract: A power module includes a first substrate, at least two power elements, at least one conductive structure and at least one leadframe. The first substrate includes a first dielectric layer and two first metal layers. The first dielectric layer has at least two concavities and two opposite surfaces, the two first metal layers are respectively disposed on the two surfaces, and the two concavities are respectively formed on the two surfaces. The two power elements are respectively embedded in the two concavities of the first dielectric layer. The two power elements are electrically connected to each other through the conductive structure. The leadframe disposed at the first substrate is electrically connected to the two power elements, and is partially extended outside the first substrate.

Abstract: A graphics processing method for three-dimensional images, applied to a first buffer for storing right-view contents and a second buffer for storing left-view contents, includes the following steps: sending drawing commands respectively related to the right-view contents and the left-view contents to a drawing engine; when a current Vsync status indicates that a display engine is not operating within a right Vsync period of a right-view frame, the drawing engine drawing the right-view contents stored in first buffer; when current Vsync status indicates that the display engine is not operating within a left Vsync period of a left-view frame, the drawing engine drawing the left-view contents stored in second buffer; during the right Vsync period of the right-view frame, the display engine displaying right-view contents stored in first buffer; and during the left Vsync period of the left-view frame, the display engine displaying left-view contents stored in second buffer.

Abstract: There are provided a recombinant silk protein derived from sea anemones, a method for producing the same, and a composition for preparing a silk fiber including same. The recombinant silk protein derived from sea anemones has sequence features similar to genetic information of a silk protein derived from spiders and silkworms. Also, a large amount of recombinant silk protein derived from sea anemones may be produced from a transformant and it has good physical properties such as strength and elasticity. Therefore, the recombinant silk protein derived from sea anemones can be usefully applied in various industrial fields in which natural silk protein can be applied, and it is expected to create new industrial fields based on its distinctive mechanical properties.

Abstract: Disclosed herein is an electrode for capacitive deionization device including an active material, a waterborne polyurethane, and a conducting agent. Disclosed herein too is a method of manufacturing the electrode and a capacitive deionization device employing the electrode. The waterborne polyurethane is a product of reaction of a polyurethane prepolymer prepared by reacting a polyol, a diisocyanate-based compound, and a dispersing agent, with a neutralizing agent and a chain extending agent.