Abstract: A memory system includes a nonvolatile memory device including a CAM (content addressable memory) region; and a controller including a random access memory which stores an initial setting parameter of the nonvolatile memory device and a control unit which controls an initializing operation for a setting parameter of the nonvolatile memory device stored in the CAM region, wherein the control unit includes a parameter determination circuit which determines whether the initializing operation has succeeded or not, by comparing a verify parameter received from the nonvolatile memory device and the initial setting parameter.

Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and a method of operating the memory system. According to the embodiments of the present disclosure, when result data obtained by derandomizing data included in a flag area is different from reference data after a random data unit is derandomized based on a seed, it is possible to detect an error occurring in the seed in a process of derandomizing the data and to prevent malfunction of firmware in advance by searching for a target seed and derandomizing the random data unit based on the target seed.

Abstract: A memory system includes a memory device including plural memory blocks divided into a system region, a user data region and a reserved region. The system region includes a first block storing original firmware and a second block storing copied firmware, and the reserved region includes a dedicated test block having an operational characteristic that substantially the same as that of the second block. The memory system includes a controller configured to access the dedicated test block for determining a status of the second block based on an operation state of the dedicated test block, and to update both the dedicated test block and the second block based on the status of the second block.

Abstract: A data storage device includes: a storage configured to store flag information on attributes, each attribute corresponding to a revision version, and firmware comprising register setting information and firmware execution code branch information for each attribute; and a controller configured to read the flag information and the firmware from the storage to execute the firmware according to the flag information.

Abstract: Provided is a 2-cyanopyrimidin-4-yl carbamate or urea derivative or pharmaceutically acceptable salt thereof, a process for the preparation thereof, and a pharmaceutical composition comprising the same. The 2-cyanopyrimidin-4-yl carbamate or urea derivative or pharmaceutically acceptable salt thereof selectively inhibits cathepsin K and therefore can be usefully applied for preventing or treating osteoporosis.

Abstract: A storage device includes a semiconductor memory device including memory blocks; and a controller configured to control the semiconductor memory device. The semiconductor memory device stores first firmware in a first memory block among the memory blocks, and stores second firmware in a second memory block among the memory blocks. The controller includes a recovery determination circuit configured to determine whether to perform a recovery operation for at least one of the first and second firmwares, based on loading times of the first and second firmwares, cumulative loading time informations for the first and second firmwares and a booting count information; and a recovery performing circuit configured to perform the recovery operation for at least one of the first and second firmwares, based on the determination of the recovery determination circuit.

Abstract: A controller may include: a ROM code register configured to generate and store a ROM code including a plurality of firmware images; and a ROM controller configured to change an operation setting of a ROM based on an operation firmware image of the plurality of firmware images, wherein each of the plurality of firmware images includes an image header including attribute information on a corresponding firmware image and image data, and wherein the operation firmware image includes, as its image header, an operation image header, which includes an operation mode field indicating whether the operation setting of the ROM is changed, and, as its image data, operation image data including information on the operation setting of the ROM.

Abstract: A data storage apparatus includes a storage configured to include a storage configured to include at least one die including a plurality of planes, wherein each of the plurality of planes contains a set of a plurality of memory blocks, each including a plurality of pages configured of a plurality of memory cells; and a controller configured to: control data input to and output from the storage according to a request received from a host apparatus, receive a plurality of read requests including respective access addresses and access sizes from the host apparatus, generate one or more paired read requests from among the plurality of read requests so that a region to be accessed in one read operation is minimized, and determine a read option for each of the paired read requests.

Abstract: A data storage device may include: a storage configured to store user data, firmware and a boot code; and a controller configured to control data exchange with the storage, and comprising an error correction code (ECC) engine configured to perform error correction during the data exchange, wherein the ECC engine stores a first parity check matrix, performs error correction on data exchanged with the storage based on the first parity check matrix during a first operation mode, and performs error correction on data exchanged with the storage based on a second parity check matrix extracted from the firmware during a second operation mode.

Abstract: A storage device includes a semiconductor memory device including memory blocks; and a controller configured to control the semiconductor memory device. The semiconductor memory device stores first firmware in a first memory block among the memory blocks, and stores second firmware in a second memory block among the memory blocks. The controller includes a recovery determination circuit configured to determine whether to perform a recovery operation for at least one of the first and second firmwares, based on loading times of the first and second firmwares, cumulative loading time informations for the first and second firmwares and a booting count information; and a recovery performing circuit configured to perform the recovery operation for at least one of the first and second firmwares, based on the determination of the recovery determination circuit.

Abstract: The present invention relates to a pharmaceutical composition for preventing or treating inflammatory bowel disease, containing, as an active ingredient, a pyridinol derivative or a pharmaceutically acceptable salt thereof. A pyridinol derivative represented by chemical formula 1 or a pharmaceutically acceptable salt thereof has an excellent colitis inhibitory effect in an inflammatory bowel disease model, and thus can be useful as a medicine for preventing or treating inflammatory bowel disease.

Abstract: A memory system includes a memory device including plural memory blocks divided into a system region, a user data region and a reserved region. The system region includes a first block storing original firmware and a second block storing copied firmware, and the reserved region includes a dedicated test block having an operational characteristic that substantially the same as that of the second block. The memory system includes a controller configured to access the dedicated test block for determining a status of the second block based on an operation state of the dedicated test block, and to update both the dedicated test block and the second block based on the status of the second block.

Abstract: A data storage apparatus includes a storage configured to include a storage configured to include at least one die including a plurality of planes, wherein each of the plurality of planes contains a set of a plurality of memory blocks, each including a plurality of pages configured of a plurality of memory cells; and a controller configured to: control data input to and output from the storage according to a request received from a host apparatus, receive a plurality of read requests including respective access addresses and access sizes from the host apparatus, generate one or more paired read requests from among the plurality of read requests so that a region to be accessed in one read operation is minimized, and determine a read option for each of the paired read requests.

Abstract: A data storage device may include: a storage configured to store user data, firmware and a boot code; and a controller configured to control data exchange with the storage, and comprising an error correction code (ECC) engine configured to perform error correction during the data exchange, wherein the ECC engine stores a first parity check matrix, performs error correction on data exchanged with the storage based on the first parity check matrix during a first operation mode, and performs error correction on data exchanged to with the storage based on a second parity check matrix extracted from the firmware during a second operation mode.

Abstract: 7-azaindolin-2-one derivatives of Formula 1 or pharmaceutically acceptable salts thereof, a pharmaceutical composition comprising them for preventing or treating a cancer, and a method for preparing them.

Abstract: A data storage device includes: a storage configured to store flag information on attributes, each attribute corresponding to a revision version, and firmware comprising register setting information and firmware execution code branch information for each attribute; and a controller configured to read the flag information and the firmware from the storage to execute the firmware according to the flag information.

Abstract: Provided herein may be a memory system and a method of operating a memory controller. The memory system may include a memory device and a memory controller. The memory device may include a plurality of memory cells and store firmware data into the memory cells. The memory controller may control an operation of the memory device. The firmware data may include a firmware code. The memory controller may execute the firmware code based on host type information.

Abstract: A controller may include: a ROM code register configured to generate and store a ROM code including a plurality of firmware images; and a ROM controller configured to change an operation setting of a ROM based on an operation firmware image of the plurality of firmware images, wherein each of the plurality of firmware images includes an image header including attribute information on a corresponding firmware image and image data, and wherein the operation firmware image includes, as its image header, an operation image header, which includes an operation mode field indicating whether the operation setting of the ROM is changed, and, as its image data, operation image data including information on the operation setting of the ROM.

Abstract: A memory system includes a nonvolatile memory device including a CAM (content addressable memory) region; and a controller including a random access memory which stores an initial setting parameter of the nonvolatile memory device and a control unit which controls an initializing operation for a setting parameter of the nonvolatile memory device stored in the CAM region, wherein the control unit includes a parameter determination circuit which determines whether the initializing operation has succeeded or not, by comparing a verify parameter received from the nonvolatile memory device and the initial setting parameter.

Abstract: A memory controller includes a read only memory (ROM) suitable for outputting a ROM code to execute firmware in response to fuse data and a control processor suitable for executing the firmware in response to the ROM code. A memory system includes the memory controller and a storage device storing data.